| Message ID | E3980B5A0D7C9243AC3486B369A6143018758DE3@BY2PRD0710MB377.namprd07.prod.outlook.com |
|---|---|
| State | New |
| Headers | show |
"Pinski, Andrew" <Andrew.Pinski@caviumnetworks.com> writes: > +;; The POP instruction is special as it does not take into account the upper > +;; 32bits and is documented that way. > +(define_insn "*popcountdi2_trunc" > + [(set (match_operand:SI 0 "register_operand" "=d") > + (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))] > + "ISA_HAS_POP" > + "pop\t%0,%1" > + [(set_attr "type" "pop") > + (set_attr "mode" "SI")]) Just crossing the "i"s really, but we'd better check TARGET_64BIT too. I realise we wouldn't expect to see truncate otherwise, but the pattern wouldn't be correct for 32-bit big-endian. OK with that change, thanks. Richard
Index: testsuite/gcc.target/mips/octeon-pop-2.c =================================================================== --- testsuite/gcc.target/mips/octeon-pop-2.c (revision 0) +++ testsuite/gcc.target/mips/octeon-pop-2.c (revision 0) @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O -march=octeon -mgp64" } */ +/* The pop instruction does not depend on the word value to be sign extended. */ +/* { dg-final { scan-assembler-not "sll\t" } } */ + +long long f(long long i) +{ + return __builtin_popcount (i); +} + Index: config/mips/mips.md =================================================================== --- config/mips/mips.md (revision 189737) +++ config/mips/mips.md (working copy) @@ -2643,6 +2643,16 @@ (define_insn "popcount<mode>2" "<d>pop\t%0,%1" [(set_attr "type" "pop") (set_attr "mode" "<MODE>")]) + +;; The POP instruction is special as it does not take into account the upper +;; 32bits and is documented that way. +(define_insn "*popcountdi2_trunc" + [(set (match_operand:SI 0 "register_operand" "=d") + (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))] + "ISA_HAS_POP" + "pop\t%0,%1" + [(set_attr "type" "pop") + (set_attr "mode" "SI")]) ;; ;; ....................
Hi, The Octeon pop instruction does not take into account the upper 32bits of the 64bit register, so its usage can be optimized when there is a truncation right before the instruction. This patch implements this small optimization. OK? Bootstrapped and tested on MIPS64-linux-gnu (Octeon) with no regressions. Thanks, Andrew Pinski * config/mips/mips.md (*popcountdi2_trunc): New pattern to handle popcount of a truncation. * testsuite/gcc.target/mips/octeon-pop-2.c: New testcase.