Patchwork [ARM,2/2] Create tune for Cortex-A15.

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Submitter Greta Yorsh
Date July 20, 2012, 3:05 p.m.
Message ID <000401cd6689$1edd1350$5c9739f0$@Yorsh@arm.com>
Download mbox | patch
Permalink /patch/172293/
State New
Headers show

Comments

Greta Yorsh - July 20, 2012, 3:05 p.m.
This patch creates a new tune_param structure for Cortex-A15. The new tune
is identical to the generic cortex tune used for Cortex-A15 before this
patch, except the field prefer_ldrd_strd is set to true. This field will be
used by subsequent patches, in particular for prologue/epilogue.

Ok for trunk?

Thanks,
Greta

Changelog

gcc/

2012-07-20  Sameera Deshpande  <sameera.deshpande@arm.com>
            Greta Yorsh  <Greta.Yorsh@arm.com>

        * config/arm/arm.c (arm_cortex_a15_tune): New tune.
        * config/arm/arm-cores.def (cortex-a15): Use new tune.
Richard Earnshaw - July 20, 2012, 3:21 p.m.
On 20/07/12 16:05, Greta Yorsh wrote:
> This patch creates a new tune_param structure for Cortex-A15. The new tune
> is identical to the generic cortex tune used for Cortex-A15 before this
> patch, except the field prefer_ldrd_strd is set to true. This field will be
> used by subsequent patches, in particular for prologue/epilogue.
> 
> Ok for trunk?
> 
> Thanks,
> Greta
> 
> Changelog
> 
> gcc/
> 
> 2012-07-20  Sameera Deshpande  <sameera.deshpande@arm.com>
>             Greta Yorsh  <Greta.Yorsh@arm.com>
> 
>         * config/arm/arm.c (arm_cortex_a15_tune): New tune.
>         * config/arm/arm-cores.def (cortex-a15): Use new tune.

Do you mean "Hum it"? :-)

OK.

R.

> 
> 
> 2-tune-cortex-a15.patch.txt
> 
> 
> diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
> index 1407771..b8d4ab6 100644
> --- a/gcc/config/arm/arm-cores.def
> +++ b/gcc/config/arm/arm-cores.def
> @@ -129,7 +129,7 @@ ARM_CORE("cortex-a5",	  cortexa5,	7A,				 FL_LDSCHED, cortex_a5)
>  ARM_CORE("cortex-a7",	  cortexa7,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
>  ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, cortex)
>  ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, cortex_a9)
> -ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
> +ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
>  ARM_CORE("cortex-r4",	  cortexr4,	7R,				 FL_LDSCHED, cortex)
>  ARM_CORE("cortex-r4f",	  cortexr4f,	7R,				 FL_LDSCHED, cortex)
>  ARM_CORE("cortex-r5",	  cortexr5,	7R,				 FL_LDSCHED | FL_ARM_DIV, cortex)
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 3f13a3d..29d1974 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -958,6 +958,18 @@ const struct tune_params arm_cortex_tune =
>    false                                         /* Prefer LDRD/STRD.  */
>  };
>  
> +const struct tune_params arm_cortex_a15_tune =
> +{
> +  arm_9e_rtx_costs,
> +  NULL,
> +  1,						/* Constant limit.  */
> +  5,						/* Max cond insns.  */
> +  ARM_PREFETCH_NOT_BENEFICIAL,
> +  false,					/* Prefer constant pool.  */
> +  arm_default_branch_cost,
> +  true                                          /* Prefer LDRD/STRD.  */
> +};
> +
>  /* Branches can be dual-issued on Cortex-A5, so conditional execution is
>     less appealing.  Set max_insns_skipped to a low value.  */
>  
>

Patch

diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 1407771..b8d4ab6 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -129,7 +129,7 @@  ARM_CORE("cortex-a5",	  cortexa5,	7A,				 FL_LDSCHED, cortex_a5)
 ARM_CORE("cortex-a7",	  cortexa7,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
 ARM_CORE("cortex-a8",	  cortexa8,	7A,				 FL_LDSCHED, cortex)
 ARM_CORE("cortex-a9",	  cortexa9,	7A,				 FL_LDSCHED, cortex_a9)
-ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex)
+ARM_CORE("cortex-a15",	  cortexa15,	7A,				 FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
 ARM_CORE("cortex-r4",	  cortexr4,	7R,				 FL_LDSCHED, cortex)
 ARM_CORE("cortex-r4f",	  cortexr4f,	7R,				 FL_LDSCHED, cortex)
 ARM_CORE("cortex-r5",	  cortexr5,	7R,				 FL_LDSCHED | FL_ARM_DIV, cortex)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3f13a3d..29d1974 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -958,6 +958,18 @@  const struct tune_params arm_cortex_tune =
   false                                         /* Prefer LDRD/STRD.  */
 };
 
+const struct tune_params arm_cortex_a15_tune =
+{
+  arm_9e_rtx_costs,
+  NULL,
+  1,						/* Constant limit.  */
+  5,						/* Max cond insns.  */
+  ARM_PREFETCH_NOT_BENEFICIAL,
+  false,					/* Prefer constant pool.  */
+  arm_default_branch_cost,
+  true                                          /* Prefer LDRD/STRD.  */
+};
+
 /* Branches can be dual-issued on Cortex-A5, so conditional execution is
    less appealing.  Set max_insns_skipped to a low value.  */