From patchwork Fri Jul 20 10:53:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 172203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 90F742C0333 for ; Fri, 20 Jul 2012 21:11:02 +1000 (EST) Received: from localhost ([::1]:33843 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SsAre-0007js-LW for incoming@patchwork.ozlabs.org; Fri, 20 Jul 2012 06:55:18 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42963) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SsAqp-0005cZ-2b for qemu-devel@nongnu.org; Fri, 20 Jul 2012 06:54:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SsAqj-0001ao-3M for qemu-devel@nongnu.org; Fri, 20 Jul 2012 06:54:26 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:51109) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SsAqi-0001Wc-U5 for qemu-devel@nongnu.org; Fri, 20 Jul 2012 06:54:21 -0400 Received: by mail-pb0-f45.google.com with SMTP id ro12so5957264pbb.4 for ; Fri, 20 Jul 2012 03:54:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=oCdIXPLSZkN34RjS0k3S0CYhkOX16NbMxcbqcEvq3y8=; b=mLpaS/wt1JALKi0UtpcriVe0RVhXBDXq/nfcXhhV3OKJWT4oabVn18n1kFY9QZ7m6b 2L7XLZRXIq1wihYWl1jTdYVrL3ASU70Dv5thRT9Mm4ydGn3CTJnbc/Itj39vzqTLeoLS 4R/q/ZmygsOLcnrICkgtecGWtXXfwKKEfRo6EigHBzZzefayOhu/DK9n47Olfk0WIAn1 B2fEnYY/t8OqqXieRciCWPzL6RMgIvkWHI+lxYC8toYWTF1LR16iMEwNjxslsiSUVBq0 gBEy29xDdQqWbI+ygh3A1fBRI9ufd2VUC88Aob/QAOFsMGWkovRgm+7R5hTkjWC5Y7Cd qQXg== Received: by 10.68.242.168 with SMTP id wr8mr12803017pbc.44.1342781660504; Fri, 20 Jul 2012 03:54:20 -0700 (PDT) Received: from yakj.usersys.redhat.com (93-34-189-113.ip51.fastwebnet.it. [93.34.189.113]) by mx.google.com with ESMTPS id oi5sm3758710pbb.39.2012.07.20.03.54.16 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 20 Jul 2012 03:54:19 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 20 Jul 2012 12:53:51 +0200 Message-Id: <1342781633-7288-6-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1342781633-7288-1-git-send-email-pbonzini@redhat.com> References: <1342781633-7288-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: "Zhang, Yang Z" Subject: [Qemu-devel] [PATCH 5/7] RTC: Add divider reset support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: "Zhang, Yang Z" The first update cycle begins one-half seconds after divider reset is removed. This feature is useful for testing. Signed-off-by: Yang Zhang Signed-off-by: Paolo Bonzini --- hw/mc146818rtc.c | 50 +++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 9 deletions(-) diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index 3a99605..1ab0dc6 100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -81,6 +81,12 @@ static void rtc_update_time(RTCState *s); static void rtc_set_cmos(RTCState *s); static inline int rtc_from_bcd(RTCState *s, int a); +static inline bool rtc_running(RTCState *s) +{ + return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && + (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); +} + static uint64_t get_guest_rtc_ns(RTCState *s) { uint64_t guest_rtc; @@ -197,11 +203,15 @@ static void check_update_timer(RTCState *s) uint64_t next_update_time; uint64_t guest_nsec; - /* From the data sheet: setting the SET bit does not prevent - * interrupts from occurring! However, it will prevent an - * alarm interrupt from occurring, because the time of day is - * not updated. + /* From the data sheet: "Holding the dividers in reset prevents + * interrupts from operating, while setting the SET bit allows" + * them to occur. However, it will prevent an alarm interrupt + * from occurring, because the time of day is not updated. */ + if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { + qemu_del_timer(s->update_timer); + return; + } if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && (s->cmos_data[RTC_REG_B] & REG_B_SET)) { qemu_del_timer(s->update_timer); @@ -266,6 +276,8 @@ static void rtc_update_timer(void *opaque) int32_t irqs = REG_C_UF; int32_t new_irqs; + assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60); + /* UIP might have been latched, update time and clear it. */ rtc_update_time(s); s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; @@ -310,12 +322,31 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) case RTC_YEAR: s->cmos_data[s->cmos_index] = data; /* if in set mode, do not update the time */ - if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + if (rtc_running(s)) { rtc_set_time(s); check_update_timer(s); } break; case RTC_REG_A: + if ((data & 0x60) == 0x60) { + if (rtc_running(s)) { + rtc_update_time(s); + } + /* What happens to UIP when divider reset is enabled is + * unclear from the datasheet. Shouldn't matter much + * though. + */ + s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; + } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && + (data & 0x70) <= 0x20) { + /* when the divider reset is removed, the first update cycle + * begins one-half second later*/ + if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + s->offset = 500000000; + rtc_set_time(s); + } + s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; + } /* UIP bit is read only */ s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); @@ -325,7 +356,7 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) case RTC_REG_B: if (data & REG_B_SET) { /* update cmos to when the rtc was stopping */ - if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + if (rtc_running(s)) { rtc_update_time(s); } /* set mode: reset UIP mode */ @@ -333,7 +364,8 @@ static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) data &= ~REG_B_UIE; } else { /* if disabling set mode, update the time */ - if (s->cmos_data[RTC_REG_B] & REG_B_SET) { + if ((s->cmos_data[RTC_REG_B] & REG_B_SET) && + (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { s->offset = get_guest_rtc_ns(s) % NSEC_PER_SEC; rtc_set_time(s); } @@ -447,7 +479,7 @@ static int update_in_progress(RTCState *s) { int64_t guest_nsec; - if (s->cmos_data[RTC_REG_B] & REG_B_SET) { + if (!rtc_running(s)) { return 0; } if (qemu_timer_pending(s->update_timer)) { @@ -484,7 +516,7 @@ static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) case RTC_YEAR: /* if not in set mode, calibrate cmos before * reading*/ - if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { + if (rtc_running(s)) { rtc_update_time(s); } ret = s->cmos_data[s->cmos_index];