From patchwork Fri Jul 20 07:50:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 172152 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A42BE2C0122 for ; Fri, 20 Jul 2012 17:52:29 +1000 (EST) Received: from localhost ([::1]:52581 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ss80h-0008BK-PZ for incoming@patchwork.ozlabs.org; Fri, 20 Jul 2012 03:52:27 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33146) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ss80R-0007xF-TA for qemu-devel@nongnu.org; Fri, 20 Jul 2012 03:52:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ss80P-0002Cg-Gr for qemu-devel@nongnu.org; Fri, 20 Jul 2012 03:52:11 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:39618) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ss80P-00029B-A2 for qemu-devel@nongnu.org; Fri, 20 Jul 2012 03:52:09 -0400 Received: by mail-pb0-f45.google.com with SMTP id ro12so5736088pbb.4 for ; Fri, 20 Jul 2012 00:52:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=AfRoqnLPZkjuSV+w5dUOZ+TXRKyMYtUbg5lHBI4/FXU=; b=c4hhhWxLVjR5jBCJAakV1qvcwxN6zYcQ1m7pT8qBqCB2fJG6X69SoOLS5Tr18Kd38G EQWXdHiYkLDp/rLUZ8q32SfwjaT7rAINABKqLVM8vM+dWmiY6qPBgkLvS0S6JWBk+8KZ qrHrjUO63tHJiIPjlUWfFGBcqi/Jt9jAa4QqRBgdk+oTTI4BEKT1dLeBHyVkcEpgrHCj PJVc6QZpV6pB2vngz0RpmAypGO+vwW2qAx8H3Qhxm2BWg9BJwu7e83OWcKN+6vP/m+7N qrZ0hzLOGOcyxre9fbDcHFRHz8thLjkqJVNAKzy8gxiblBkCt0gC0JfQFDjjPetkL9Wl 2Ehw== Received: by 10.68.241.41 with SMTP id wf9mr11842056pbc.41.1342770728893; Fri, 20 Jul 2012 00:52:08 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id rd7sm3467005pbc.70.2012.07.20.00.52.03 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 20 Jul 2012 00:52:07 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Fri, 20 Jul 2012 15:50:41 +0800 Message-Id: <1342770653-11162-4-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342770653-11162-1-git-send-email-proljc@gmail.com> References: <1342770653-11162-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Subject: [Qemu-devel] [PATCH v10 03/15] target-or32: Add interrupt support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add OpenRISC interrupt support. Signed-off-by: Jia Liu --- cpu-exec.c | 17 +++++++++++ target-openrisc/Makefile.objs | 2 +- target-openrisc/cpu.h | 8 ++++- target-openrisc/helper.h | 25 ++++++++++++++++ target-openrisc/interrupt.c | 44 ++++++++++++++++++++++++++++ target-openrisc/interrupt_helper.c | 57 ++++++++++++++++++++++++++++++++++++ 6 files changed, 151 insertions(+), 2 deletions(-) create mode 100644 target-openrisc/helper.h create mode 100644 target-openrisc/interrupt_helper.c diff --git a/cpu-exec.c b/cpu-exec.c index bc47114..543460c 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -388,6 +388,23 @@ int cpu_exec(CPUArchState *env) do_interrupt(env); next_tb = 0; } +#elif defined(TARGET_OPENRISC) + { + int idx = -1; + if ((interrupt_request & CPU_INTERRUPT_HARD) + && (env->sr & SR_IEE)) { + idx = EXCP_INT; + } + if ((interrupt_request & CPU_INTERRUPT_TIMER) + && (env->sr & SR_TEE)) { + idx = EXCP_TICK; + } + if (idx >= 0) { + env->exception_index = idx; + do_interrupt(env); + next_tb = 0; + } + } #elif defined(TARGET_SPARC) if (interrupt_request & CPU_INTERRUPT_HARD) { if (cpu_interrupts_enabled(env) && diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.objs index ef933ef..74c4b8d 100644 --- a/target-openrisc/Makefile.objs +++ b/target-openrisc/Makefile.objs @@ -1,3 +1,3 @@ obj-$(CONFIG_SOFTMMU) += machine.o obj-y += cpu.o interrupt.o mmu.o translate.o -obj-y += mmu_helper.o +obj-y += interrupt_helper.o mmu_helper.o diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 9423e77..51013f3 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -83,6 +83,9 @@ enum { /* Internal flags, delay slot flag */ #define D_FLAG 1 +/* Interrupt */ +#define NR_IRQS 32 + /* Registers */ enum { R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, @@ -309,6 +312,7 @@ typedef struct CPUOpenRISCState { uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ #endif + void *irq[32]; /* Interrupt irq input */ } CPUOpenRISCState; /** @@ -392,9 +396,11 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env) return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; } +#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 static inline bool cpu_has_work(CPUOpenRISCState *env) { - return true; + return env->interrupt_request & (CPU_INTERRUPT_HARD | + CPU_INTERRUPT_TIMER); } #include "exec-all.h" diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h new file mode 100644 index 0000000..7ced5ea --- /dev/null +++ b/target-openrisc/helper.h @@ -0,0 +1,25 @@ +/* + * OpenRISC helper defines + * + * Copyright (c) 2011-2012 Jia Liu + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "def-helper.h" + +/* interrupt */ +DEF_HELPER_FLAGS_1(rfe, 0, void, env) + +#include "def-helper.h" diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 7a9ee0b..642da7d 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -27,4 +27,48 @@ void do_interrupt(CPUOpenRISCState *env) { +#ifndef CONFIG_USER_ONLY + if (env->flags & D_FLAG) { /* Delay Slot insn */ + env->flags &= ~D_FLAG; + env->sr |= SR_DSX; + if (env->exception_index == EXCP_TICK || + env->exception_index == EXCP_INT || + env->exception_index == EXCP_SYSCALL || + env->exception_index == EXCP_FPE) { + env->epcr = env->jmp_pc; + } else { + env->epcr = env->pc - 4; + } + } else { + if (env->exception_index == EXCP_TICK || + env->exception_index == EXCP_INT || + env->exception_index == EXCP_SYSCALL || + env->exception_index == EXCP_FPE) { + env->epcr = env->npc; + } else { + env->epcr = env->pc; + } + } + + /* For machine-state changed between user-mode and supervisor mode, + we need flush TLB when we enter&exit EXCP. */ + tlb_flush(env, 1); + + env->esr = env->sr; + env->sr &= ~SR_DME; + env->sr &= ~SR_IME; + env->sr |= SR_SM; + env->sr &= ~SR_IEE; + env->sr &= ~SR_TEE; + env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; + env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; + + if (env->exception_index > 0 && env->exception_index < EXCP_NR) { + env->pc = (env->exception_index << 8); + } else { + cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index); + } +#endif + + env->exception_index = -1; } diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c new file mode 100644 index 0000000..79f5afe --- /dev/null +++ b/target-openrisc/interrupt_helper.c @@ -0,0 +1,57 @@ +/* + * OpenRISC interrupt helper routines + * + * Copyright (c) 2011-2012 Jia Liu + * Feng Gao + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "cpu.h" +#include "helper.h" + +void HELPER(rfe)(CPUOpenRISCState *env) +{ + OpenRISCCPU *cpu = OPENRISC_CPU(ENV_GET_CPU(env)); +#ifndef CONFIG_USER_ONLY + int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^ + (cpu->env.esr & (SR_SM | SR_IME | SR_DME)); +#endif + cpu->env.pc = cpu->env.epcr; + cpu->env.npc = cpu->env.epcr; + cpu->env.sr = cpu->env.esr; + +#ifndef CONFIG_USER_ONLY + if (cpu->env.sr & SR_DME) { + cpu->env.tlb->cpu_openrisc_map_address_data = + &cpu_openrisc_get_phys_data; + } else { + cpu->env.tlb->cpu_openrisc_map_address_data = + &cpu_openrisc_get_phys_nommu; + } + + if (cpu->env.sr & SR_IME) { + cpu->env.tlb->cpu_openrisc_map_address_code = + &cpu_openrisc_get_phys_code; + } else { + cpu->env.tlb->cpu_openrisc_map_address_code = + &cpu_openrisc_get_phys_nommu; + } + + if (need_flush_tlb) { + tlb_flush(&cpu->env, 1); + } +#endif + cpu->env.interrupt_request |= CPU_INTERRUPT_EXITTB; +}