Patchwork powerpc/85xx: Fix sram_offset parameter type

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Submitter Claudiu Manoil
Date July 19, 2012, 10:28 a.m.
Message ID <1342693696-29734-1-git-send-email-claudiu.manoil@freescale.com>
Download mbox | patch
Permalink /patch/171920/
State Superseded
Delegated to: Kumar Gala
Headers show

Comments

Claudiu Manoil - July 19, 2012, 10:28 a.m.
The sram_offset parameter represents a physical address
and should be of type phys_addr_t. As part of this fix,
the extraction of sram_params is being cleaned-up and
fixed.
This patch fixes now the case when the offset value of
0xfff00000 was being rejected by the driver (returning
-EINVAL), although this is a valid offset value.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
 arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h |    4 +-
 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c     |   39 ++++++++++------------------
 2 files changed, 16 insertions(+), 27 deletions(-)
Kumar Gala - July 19, 2012, 12:07 p.m.
On Jul 19, 2012, at 5:28 AM, Claudiu Manoil wrote:

> The sram_offset parameter represents a physical address
> and should be of type phys_addr_t. As part of this fix,
> the extraction of sram_params is being cleaned-up and
> fixed.
> This patch fixes now the case when the offset value of
> 0xfff00000 was being rejected by the driver (returning
> -EINVAL), although this is a valid offset value.
> 
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
> ---
> arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h |    4 +-
> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c     |   39 ++++++++++------------------
> 2 files changed, 16 insertions(+), 27 deletions(-)
> 
> diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
> index 60c9c0b..a4ce9b8 100644
> --- a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
> +++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
> @@ -1,5 +1,5 @@
> /*
> - * Copyright 2009-2010 Freescale Semiconductor, Inc
> + * Copyright 2009-2010 2012 Freescale Semiconductor, Inc

we normally do 2009-2010, 2012

>  *
>  * QorIQ based Cache Controller Memory Mapped Registers
>  *
> @@ -91,7 +91,7 @@ struct mpc85xx_l2ctlr {
> 
> struct sram_parameters {
> 	unsigned int sram_size;
> -	uint64_t sram_offset;
> +	phys_addr_t sram_offset;
> };
> 
> 

- k
Claudiu Manoil - July 26, 2012, 12:39 p.m.
On 7/19/2012 3:07 PM, Kumar Gala wrote:
>
> On Jul 19, 2012, at 5:28 AM, Claudiu Manoil wrote:
>
>> The sram_offset parameter represents a physical address
>> and should be of type phys_addr_t. As part of this fix,
>> the extraction of sram_params is being cleaned-up and
>> fixed.
>> This patch fixes now the case when the offset value of
>> 0xfff00000 was being rejected by the driver (returning
>> -EINVAL), although this is a valid offset value.
>>
>> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
>> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
>> ---
>> arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h |    4 +-
>> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c     |   39 ++++++++++------------------
>> 2 files changed, 16 insertions(+), 27 deletions(-)
>>
>> diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
>> index 60c9c0b..a4ce9b8 100644
>> --- a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
>> +++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
>> @@ -1,5 +1,5 @@
>> /*
>> - * Copyright 2009-2010 Freescale Semiconductor, Inc
>> + * Copyright 2009-2010 2012 Freescale Semiconductor, Inc
>
> we normally do 2009-2010, 2012
>
Hi Kumar,

Should I re-spin this patch, with the copyright year formatted per your 
suggestion above?

Thanks,
claudiu
Kumar Gala - July 26, 2012, 1:18 p.m.
On Jul 26, 2012, at 7:39 AM, Claudiu Manoil wrote:

> On 7/19/2012 3:07 PM, Kumar Gala wrote:
>> 
>> On Jul 19, 2012, at 5:28 AM, Claudiu Manoil wrote:
>> 
>>> The sram_offset parameter represents a physical address
>>> and should be of type phys_addr_t. As part of this fix,
>>> the extraction of sram_params is being cleaned-up and
>>> fixed.
>>> This patch fixes now the case when the offset value of
>>> 0xfff00000 was being rejected by the driver (returning
>>> -EINVAL), although this is a valid offset value.
>>> 
>>> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
>>> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
>>> ---
>>> arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h |    4 +-
>>> arch/powerpc/sysdev/fsl_85xx_l2ctlr.c     |   39 ++++++++++------------------
>>> 2 files changed, 16 insertions(+), 27 deletions(-)
>>> 
>>> diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
>>> index 60c9c0b..a4ce9b8 100644
>>> --- a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
>>> +++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
>>> @@ -1,5 +1,5 @@
>>> /*
>>> - * Copyright 2009-2010 Freescale Semiconductor, Inc
>>> + * Copyright 2009-2010 2012 Freescale Semiconductor, Inc
>> 
>> we normally do 2009-2010, 2012
>> 
> Hi Kumar,
> 
> Should I re-spin this patch, with the copyright year formatted per your suggestion above?

please do

- k

Patch

diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
index 60c9c0b..a4ce9b8 100644
--- a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc
+ * Copyright 2009-2010 2012 Freescale Semiconductor, Inc
  *
  * QorIQ based Cache Controller Memory Mapped Registers
  *
@@ -91,7 +91,7 @@  struct mpc85xx_l2ctlr {
 
 struct sram_parameters {
 	unsigned int sram_size;
-	uint64_t sram_offset;
+	phys_addr_t sram_offset;
 };
 
 extern int instantiate_cache_sram(struct platform_device *dev,
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index 611bb4b..d65e785 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010 2012 Freescale Semiconductor, Inc.
  *
  * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
  *
@@ -31,24 +31,21 @@  static char *sram_size;
 static char *sram_offset;
 struct mpc85xx_l2ctlr __iomem *l2ctlr;
 
-static long get_cache_sram_size(void)
+static int get_cache_sram_params(struct sram_parameters *sram_params)
 {
-	unsigned long val;
+	unsigned long long addr;
+	unsigned int size;
 
-	if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0))
+	if (!sram_size || (kstrtouint(sram_size, 0, &size) < 0))
 		return -EINVAL;
 
-	return val;
-}
-
-static long get_cache_sram_offset(void)
-{
-	unsigned long val;
-
-	if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0))
+	if (!sram_offset || (kstrtoull(sram_offset, 0, &addr) < 0))
 		return -EINVAL;
 
-	return val;
+	sram_params->sram_offset = addr;
+	sram_params->sram_size = size;
+
+	return 0;
 }
 
 static int __init get_size_from_cmdline(char *str)
@@ -93,17 +90,9 @@  static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
 	}
 	l2cache_size = *prop;
 
-	sram_params.sram_size  = get_cache_sram_size();
-	if ((int)sram_params.sram_size <= 0) {
-		dev_err(&dev->dev,
-			"Entire L2 as cache, Aborting Cache-SRAM stuff\n");
-		return -EINVAL;
-	}
-
-	sram_params.sram_offset  = get_cache_sram_offset();
-	if ((int64_t)sram_params.sram_offset <= 0) {
+	if (get_cache_sram_params(&sram_params)) {
 		dev_err(&dev->dev,
-			"Entire L2 as cache, provide a valid sram offset\n");
+			"Entire L2 as cache, provide valid sram offset and size\n");
 		return -EINVAL;
 	}
 
@@ -125,14 +114,14 @@  static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
 	 * Write bits[0-17] to srbar0
 	 */
 	out_be32(&l2ctlr->srbar0,
-		sram_params.sram_offset & L2SRAM_BAR_MSK_LO18);
+		lower_32_bits(sram_params.sram_offset) & L2SRAM_BAR_MSK_LO18);
 
 	/*
 	 * Write bits[18-21] to srbare0
 	 */
 #ifdef CONFIG_PHYS_64BIT
 	out_be32(&l2ctlr->srbarea0,
-		(sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4);
+		upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4);
 #endif
 
 	clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);