Patchwork Intrinsics for ADCX, ADOX, RDSEED and PREFETCHW

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Submitter Uros Bizjak
Date July 19, 2012, 10:21 a.m.
Message ID <CAFULd4bTGZTke7p_LeqqiweOce0KaxWtCwYfNFzMdD7cr21PAA@mail.gmail.com>
Download mbox | patch
Permalink /patch/171917/
State New
Headers show

Comments

Uros Bizjak - July 19, 2012, 10:21 a.m.
On Thu, Jul 19, 2012 at 11:51 AM, Jakub Jelinek <jakub@redhat.com> wrote:

>> >> You have a mnemonic clash here. prefetchw is not good name for a new
>> >> instruction, it clashes with existing 3dnow name. Intel will need to
>> >> fix the spec, you probably won't be able to change prefetchw encoding
>> >> in binutils.
>> >
>> > From what I understand, Intel is using the same encoding of that insn as
>> > 3dNOW!, so there is no clash, just the same insn is now enabled by two ISAs
>> > (3dNOW! and this new CPUID prfchw bit).
>>
>> I see. Then please review prefetch changes to not change existing
>> functionality (i.e. -m3dnow should work as now, while -m3dnow -mprfchw
>> can emit new instructions everywhere). However, do not change existing
>> mm3dnow.h header.
>
> I think it is fine to change existing mm3dnow.h header, but not in the way
> it has been changed in the patch.  The thing is that unlike the newly added
> intrinsics headers, mm3dnow.h is still publicly includable header, and just
> including that header should work properly, so mm3dnow.h has to include
> prftchwintrin.h, which should be allowed to be included from x86intrin.h
> as well as mm3dnow.h, and that header should have guards, so that if both
> x86intrin.h is included and mm3dnow.h too (the latter first),
> prftchwintrin.h isn't included in twice.

Following (untested) patch solves insn generation issue:

--cut here--
--cut here--

Uros.
>
>         Jakub

Patch

Index: i386.md
===================================================================
--- i386.md     (revision 189643)
+++ i386.md     (working copy)
@@ -17662,7 +17662,8 @@ 
      supported by SSE counterpart or the SSE prefetch is not available
      (K6 machines).  Otherwise use SSE prefetch as it allows specifying
      of locality.  */
-  if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
+  if (rw && (TARGET_3DNOW || TARGET_PRFCHW)
+      || (TARGET_3DNOW && !TARGET_PREFETCH_SSE))
     operands[2] = GEN_INT (3);
   else
     operands[1] = const0_rtx;
@@ -17693,10 +17694,13 @@ 
   [(prefetch (match_operand:P 0 "address_operand" "p")
             (match_operand:SI 1 "const_int_operand" "n")
             (const_int 3))]
-  "TARGET_3DNOW"
+  "TARGET_3DNOW || TARGET_PRFCHW"
 {
   if (INTVAL (operands[1]) == 0)
-    return "prefetch\t%a0";
+    {
+      gcc_assert (!TARGET_PREFETCH_SSE);
+      return "prefetch\t%a0";
+    }
   else
     return "prefetchw\t%a0";
 }
Index: i386.c
===================================================================
--- i386.c      (revision 189643)
+++ i386.c      (working copy)
@@ -3647,11 +3647,11 @@  ix86_option_override_internal (bool main_args_p)

   /* Turn on MMX builtins for -msse.  */
   if (TARGET_SSE)
-    {
-      ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
-      x86_prefetch_sse = true;
-    }
+    ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;

+  if (TARGET_SSE || TARGET_PRFCHW)
+    x86_prefetch_sse = true;
+
   /* Turn on popcnt instruction for -msse4.2 or -mabm.  */
   if (TARGET_SSE4_2 || TARGET_ABM)
     ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;