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[165.228.126.9]) by mx.google.com with ESMTPS id hz10sm592316pbc.32.2012.07.18.17.35.15 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 18 Jul 2012 17:35:17 -0700 (PDT) From: Alexey Kardashevskiy To: "Michael S. Tsirkin" Date: Thu, 19 Jul 2012 10:35:07 +1000 Message-Id: <1342658107-22814-1-git-send-email-aik@ozlabs.ru> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <20120718152355.GA1421@redhat.com> References: <20120718152355.GA1421@redhat.com> X-Gm-Message-State: ALoCoQkEijiQNJQbe3r9sTFw90YeMhnUfp7R4EoIedb90uyBnfozNdsTDKYVWAl1VgF31/ZITePQ X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexey Kardashevskiy , qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH] msi/msix: added API to set MSI message address and data X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added (msi|msix)_set_message() function for whoever might want to use them. Currently msi_notify()/msix_notify() write to these vectors to signal the guest about an interrupt so the correct values have to written there by the guest or QEMU. For example, POWER guest never initializes MSI/MSIX vectors, instead it uses RTAS hypercalls. So in order to support MSIX for virtio-pci on POWER we have to initialize MSI/MSIX message from QEMU. Signed-off-by: Alexey Kardashevskiy --- hw/msi.c | 17 +++++++++++++++++ hw/msi.h | 1 + hw/msix.c | 13 +++++++++++++ hw/msix.h | 1 + 4 files changed, 32 insertions(+) diff --git a/hw/msi.c b/hw/msi.c index 5233204..e2273a0 100644 --- a/hw/msi.c +++ b/hw/msi.c @@ -105,6 +105,23 @@ static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit) return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32); } +/* + * Special API for POWER to configure the vectors through + * a side channel. Should never be used by devices. + */ +void msi_set_message(PCIDevice *dev, MSIMessage msg) +{ + uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev)); + bool msi64bit = flags & PCI_MSI_FLAGS_64BIT; + + if (msi64bit) { + pci_set_quad(dev->config + msi_address_lo_off(dev), msg.address); + } else { + pci_set_long(dev->config + msi_address_lo_off(dev), msg.address); + } + pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data); +} + bool msi_enabled(const PCIDevice *dev) { return msi_present(dev) && diff --git a/hw/msi.h b/hw/msi.h index 75747ab..6ec1f99 100644 --- a/hw/msi.h +++ b/hw/msi.h @@ -31,6 +31,7 @@ struct MSIMessage { extern bool msi_supported; +void msi_set_message(PCIDevice *dev, MSIMessage msg); bool msi_enabled(const PCIDevice *dev); int msi_init(struct PCIDevice *dev, uint8_t offset, unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask); diff --git a/hw/msix.c b/hw/msix.c index fd9ea95..800fc32 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -37,6 +37,19 @@ static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector) return msg; } +/* + * Special API for POWER to configure the vectors through + * a side channel. Should never be used by devices. + */ +void msix_set_message(PCIDevice *dev, int vector, struct MSIMessage msg) +{ + uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE; + + pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, msg.address); + pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, msg.data); + table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; +} + static uint8_t msix_pending_mask(int vector) { return 1 << (vector % 8); diff --git a/hw/msix.h b/hw/msix.h index 1786e27..15211cb 100644 --- a/hw/msix.h +++ b/hw/msix.h @@ -4,6 +4,7 @@ #include "qemu-common.h" #include "pci.h" +void msix_set_message(PCIDevice *dev, int vector, MSIMessage msg); int msix_init(PCIDevice *dev, unsigned short nentries, MemoryRegion *table_bar, uint8_t table_bar_nr, unsigned table_offset, MemoryRegion *pba_bar,