Patchwork target-xtensa: fix big-endian BBS/BBC implementation

login
register
mail settings
Submitter Max Filippov
Date July 17, 2012, 7:45 p.m.
Message ID <1342554323-29147-1-git-send-email-jcmvbkbc@gmail.com>
Download mbox | patch
Permalink /patch/171548/
State New
Headers show

Comments

Max Filippov - July 17, 2012, 7:45 p.m.
Quote from ISA, 2.1:

For most Xtensa instructions, bit numbering is irrelevant; only the BBC
and BBS instructions assign bit numbers to values on which the processor
operates. The BBC/BBS instructions use big-endian bit ordering (0 is the
most-significant bit) on a big-endian processor configuration.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
This is also applicable to qemu-stable 1.0 and 1.1

 target-xtensa/translate.c |   16 ++++++++++++++--
 1 files changed, 14 insertions(+), 2 deletions(-)
Blue Swirl - July 28, 2012, 12:16 p.m.
Thanks, applied.

On Tue, Jul 17, 2012 at 7:45 PM, Max Filippov <jcmvbkbc@gmail.com> wrote:
> Quote from ISA, 2.1:
>
> For most Xtensa instructions, bit numbering is irrelevant; only the BBC
> and BBS instructions assign bit numbers to values on which the processor
> operates. The BBC/BBS instructions use big-endian bit ordering (0 is the
> most-significant bit) on a big-endian processor configuration.
>
> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
> ---
> This is also applicable to qemu-stable 1.0 and 1.1
>
>  target-xtensa/translate.c |   16 ++++++++++++++--
>  1 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
> index b883e6b..1900bd5 100644
> --- a/target-xtensa/translate.c
> +++ b/target-xtensa/translate.c
> @@ -2366,10 +2366,18 @@ static void disas_xtensa_insn(DisasContext *dc)
>              case 5: /*BBC*/ /*BBS*/
>                  gen_window_check2(dc, RRI8_S, RRI8_T);
>                  {
> -                    TCGv_i32 bit = tcg_const_i32(1);
> +#ifdef TARGET_WORDS_BIGENDIAN
> +                    TCGv_i32 bit = tcg_const_i32(0x80000000);
> +#else
> +                    TCGv_i32 bit = tcg_const_i32(0x00000001);
> +#endif
>                      TCGv_i32 tmp = tcg_temp_new_i32();
>                      tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
> +#ifdef TARGET_WORDS_BIGENDIAN
> +                    tcg_gen_shr_i32(bit, bit, tmp);
> +#else
>                      tcg_gen_shl_i32(bit, bit, tmp);
> +#endif
>                      tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
>                      gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
>                      tcg_temp_free(tmp);
> @@ -2383,7 +2391,11 @@ static void disas_xtensa_insn(DisasContext *dc)
>                  {
>                      TCGv_i32 tmp = tcg_temp_new_i32();
>                      tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
> -                            1 << (((RRI8_R & 1) << 4) | RRI8_T));
> +#ifdef TARGET_WORDS_BIGENDIAN
> +                            0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
> +#else
> +                            0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
> +#endif
>                      gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
>                      tcg_temp_free(tmp);
>                  }
> --
> 1.7.7.6
>

Patch

diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index b883e6b..1900bd5 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2366,10 +2366,18 @@  static void disas_xtensa_insn(DisasContext *dc)
             case 5: /*BBC*/ /*BBS*/
                 gen_window_check2(dc, RRI8_S, RRI8_T);
                 {
-                    TCGv_i32 bit = tcg_const_i32(1);
+#ifdef TARGET_WORDS_BIGENDIAN
+                    TCGv_i32 bit = tcg_const_i32(0x80000000);
+#else
+                    TCGv_i32 bit = tcg_const_i32(0x00000001);
+#endif
                     TCGv_i32 tmp = tcg_temp_new_i32();
                     tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
+#ifdef TARGET_WORDS_BIGENDIAN
+                    tcg_gen_shr_i32(bit, bit, tmp);
+#else
                     tcg_gen_shl_i32(bit, bit, tmp);
+#endif
                     tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
                     tcg_temp_free(tmp);
@@ -2383,7 +2391,11 @@  static void disas_xtensa_insn(DisasContext *dc)
                 {
                     TCGv_i32 tmp = tcg_temp_new_i32();
                     tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
-                            1 << (((RRI8_R & 1) << 4) | RRI8_T));
+#ifdef TARGET_WORDS_BIGENDIAN
+                            0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
+#else
+                            0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
+#endif
                     gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
                     tcg_temp_free(tmp);
                 }