From patchwork Tue Jul 17 12:30:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerd Hoffmann X-Patchwork-Id: 171418 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A2BF12C0081 for ; Tue, 17 Jul 2012 23:04:59 +1000 (EST) Received: from localhost ([::1]:41611 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sr6wS-0003Zw-Oa for incoming@patchwork.ozlabs.org; Tue, 17 Jul 2012 08:31:52 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40624) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sr6vg-0001i0-A4 for qemu-devel@nongnu.org; Tue, 17 Jul 2012 08:31:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sr6vY-0007mL-C9 for qemu-devel@nongnu.org; Tue, 17 Jul 2012 08:31:04 -0400 Received: from mx1.redhat.com ([209.132.183.28]:16656) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sr6vY-0007la-3v for qemu-devel@nongnu.org; Tue, 17 Jul 2012 08:30:56 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q6HCUs5i032294 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 17 Jul 2012 08:30:54 -0400 Received: from rincewind.home.kraxel.org (ovpn-116-24.ams2.redhat.com [10.36.116.24]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q6HCUrdn015355; Tue, 17 Jul 2012 08:30:54 -0400 Received: by rincewind.home.kraxel.org (Postfix, from userid 500) id DC52240CD4; Tue, 17 Jul 2012 14:30:52 +0200 (CEST) From: Gerd Hoffmann To: qemu-devel@nongnu.org, seabios@seabios.org Date: Tue, 17 Jul 2012 14:30:52 +0200 Message-Id: <1342528252-11470-5-git-send-email-kraxel@redhat.com> In-Reply-To: <1342528252-11470-1-git-send-email-kraxel@redhat.com> References: <1342528252-11470-1-git-send-email-kraxel@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: Gerd Hoffmann Subject: [Qemu-devel] [rfc patch qemu 4/4] wakeup: uhci support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement the (intel-specific) pci configuration register 0xc4, which is a bitmask saying which ports are allowed to wakeup the system. Also assign gpe bit 0x0b (used only in case uhci handles device 01.2). Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-uhci.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index 8f652d2..b2da21d 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -32,6 +32,7 @@ #include "iov.h" #include "dma.h" #include "trace.h" +#include "sysemu.h" //#define DEBUG //#define DEBUG_DUMP_DATA @@ -129,6 +130,7 @@ struct UHCIState { uint32_t fl_base_addr; /* frame list base address */ uint8_t sof_timing; uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ + uint8_t system_wakeup; int64_t expire_time; QEMUTimer *frame_timer; QEMUBH *bh; @@ -665,6 +667,22 @@ static void uhci_wakeup(USBPort *port1) } } +static void uhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep) +{ + USBPort *port1 = ep->dev->port; + UHCIState *s = port1->opaque; + + if (!(s->system_wakeup & (1 << port1->index))) { + return; + } + if (s->dev.devfn == PCI_DEVFN(1, 2)) { + /* piix3/4 chipset uhci controller */ + qemu_system_wakeup_request(QEMU_WAKEUP_REASON_GPE_b); + } else { + qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER); + } +} + static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) { USBDevice *dev; @@ -1181,6 +1199,7 @@ static USBPortOps uhci_port_ops = { }; static USBBusOps uhci_bus_ops = { + .wakeup_endpoint = uhci_wakeup_endpoint, }; static int usb_uhci_common_initfn(PCIDevice *dev) @@ -1242,6 +1261,17 @@ static int usb_uhci_common_initfn(PCIDevice *dev) return 0; } +static void usb_uhci_intel_write_config(PCIDevice *dev, uint32_t addr, + uint32_t val, int len) +{ + UHCIState *s = DO_UPCAST(UHCIState, dev, dev); + + pci_default_write_config(dev, addr, val, len); + if (addr == 0xc4) { + s->system_wakeup = val; + } +} + static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) { UHCIState *s = DO_UPCAST(UHCIState, dev, dev); @@ -1279,6 +1309,7 @@ static void piix3_uhci_class_init(ObjectClass *klass, void *data) k->init = usb_uhci_common_initfn; k->exit = usb_uhci_exit; + k->config_write = usb_uhci_intel_write_config; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; k->revision = 0x01; @@ -1301,6 +1332,7 @@ static void piix4_uhci_class_init(ObjectClass *klass, void *data) k->init = usb_uhci_common_initfn; k->exit = usb_uhci_exit; + k->config_write = usb_uhci_intel_write_config; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; k->revision = 0x01; @@ -1344,6 +1376,7 @@ static void ich9_uhci1_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->init = usb_uhci_common_initfn; + k->config_write = usb_uhci_intel_write_config; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; k->revision = 0x03; @@ -1365,6 +1398,7 @@ static void ich9_uhci2_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->init = usb_uhci_common_initfn; + k->config_write = usb_uhci_intel_write_config; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; k->revision = 0x03; @@ -1386,6 +1420,7 @@ static void ich9_uhci3_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); k->init = usb_uhci_common_initfn; + k->config_write = usb_uhci_intel_write_config; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; k->revision = 0x03;