Patchwork [rfc,seabios,3/3] wakeup: uhci

login
register
mail settings
Submitter Gerd Hoffmann
Date July 17, 2012, 12:31 p.m.
Message ID <1342528262-11548-4-git-send-email-kraxel@redhat.com>
Download mbox | patch
Permalink /patch/171415/
State New
Headers show

Comments

Gerd Hoffmann - July 17, 2012, 12:31 p.m.
Windup gpe bit 0x0b for s3 wakeup.  Also add methods to update
the pci config space register 0xc4 which enables/disables wakeup
per usb port.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 src/acpi-dsdt.dsl |   41 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+), 0 deletions(-)

Patch

diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
index 03efbfd..07e531d 100644
--- a/src/acpi-dsdt.dsl
+++ b/src/acpi-dsdt.dsl
@@ -312,6 +312,46 @@  DefinitionBlock (
 
 
 /****************************************************************
+ * USB
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        Device (UHCI) {
+            Name (_ADR, 0x00010002)
+
+            OperationRegion (U0CS, PCI_Config, 0xC4, 0x04)
+            Field (U0CS, DWordAcc, NoLock, Preserve)
+            {
+                U0EN,   2,
+                        Offset (0x04)
+            }
+
+            Name (_S3D, 0x03)
+            Name (_S3W, 0x03)
+
+            /* Power Resources for Wake */
+            Name(_PRW, Package(2) {
+                0x0b,  // GPE bit
+                0x03,  // S3
+            })
+
+            /* Power State Wake */
+            Method (_PSW, 1, NotSerialized)
+            {
+                If (Arg0)
+                {
+                    Store (0x03, U0EN)
+                }
+                Else
+                {
+                    Store (0x00, U0EN)
+                }
+            }
+        }
+    }
+
+
+/****************************************************************
  * PIIX3 ISA bridge
  ****************************************************************/
 
@@ -803,6 +843,7 @@  DefinitionBlock (
             Return(0x01)
         }
         Method(_L0B) {
+            Notify(\_SB.PCI0.UHCI, 0x80)
             Return(0x01)
         }
         Method(_L0C) {