From patchwork Tue Jul 17 11:55:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dong Aisheng X-Patchwork-Id: 171401 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AAD432C0084 for ; Tue, 17 Jul 2012 22:09:37 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Sr6XK-0005VC-94; Tue, 17 Jul 2012 12:05:54 +0000 Received: from co1ehsobe003.messaging.microsoft.com ([216.32.180.186] helo=co1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Sr6XE-0005TZ-Q0 for linux-arm-kernel@lists.infradead.org; Tue, 17 Jul 2012 12:05:50 +0000 Received: from mail78-co1-R.bigfish.com (10.243.78.234) by CO1EHSOBE011.bigfish.com (10.243.66.74) with Microsoft SMTP Server id 14.1.225.23; Tue, 17 Jul 2012 12:05:46 +0000 Received: from mail78-co1 (localhost [127.0.0.1]) by mail78-co1-R.bigfish.com (Postfix) with ESMTP id 6DED1C80277; Tue, 17 Jul 2012 12:05:46 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 1 X-BigFish: VS1(zz98dI1432Izz1202h1082kzzz2dh2a8h668h839h944hd25hf0ah107ah) Received: from mail78-co1 (localhost.localdomain [127.0.0.1]) by mail78-co1 (MessageSwitch) id 1342526744530479_19001; Tue, 17 Jul 2012 12:05:44 +0000 (UTC) Received: from CO1EHSMHS012.bigfish.com (unknown [10.243.78.230]) by mail78-co1.bigfish.com (Postfix) with ESMTP id 75D8E200044; Tue, 17 Jul 2012 12:05:44 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS012.bigfish.com (10.243.66.22) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 17 Jul 2012 12:05:43 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.298.5; Tue, 17 Jul 2012 07:05:42 -0500 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q6HC5cA0020740; Tue, 17 Jul 2012 05:05:38 -0700 Date: Tue, 17 Jul 2012 19:55:32 +0800 From: Dong Aisheng To: Andreas Gretler Subject: Re: MX28EVK mainline 3.5-Patchs-3.5-rc5 sgtl5000 record not working Message-ID: <20120717115531.GA11024@shlinux2.ap.freescale.net> References: <20120711031446.GB14060@S2101-09.ap.freescale.net> <20120711085244.GA22640@shlinux2.ap.freescale.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginatorOrg: freescale.com X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.180.186 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Dong Aisheng , Shawn Guo , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org On Mon, Jul 16, 2012 at 07:23:42PM +0800, Andreas Gretler wrote: > > I can see the same problem at my side. > > Usually it's caused by clock issue. > > I will try to fix it tomorrow when have time. > > > > Regards > > Dong Aisheng > > > Hi, > > i did a bit more research on it. Before the change to common clock > framework, it seems that I can toggle the headphone and adc from Mic > to Line in. The headphone toggle to direct output works, but > unfortunately if i toggle the ADC input source to Line-In the > recorded sound is only a noisy signal. > > I test several past version, but I can not find a version where the > recording function for Line-In works. > > It seems it's broken for a long time. I tried 3.3 kernel, with adding below change the record can work( can hear some noise, however, that's another issue of codec driver). > I try to understand the saif-code, but i does not understand why not > all clk_enable are replaced by clk_prepare_enable. Can anyone explain clk_prepare_enable can not be called in atomic context. So in trigger function, we call clk_enable instead. > that? I replaced the clk_enable clk_prepare_enableand the board does > not crash, but there is an input/output error. > It seems dma did not work properly. > /* > * If the saif's master is not himself, we also need to enable > * itself clk for its internal basic logic to work. > */ > if (saif != master_saif) { > clk_enable(saif->clk); > __raw_writel(BM_SAIF_CTRL_RUN, > saif->base + SAIF_CTRL + MXS_SET_ADDR); > } > > > Another question is about the initial clock rate for the saif internal > logic. Befor the clock_mx28.c was deleted, there was an > clk_set_rate(&saif1_clk, 24000000); for internal logic. Where it is > now being made? I did not found it. That should be added. I tried, but still did not work. Still did not have too much time to dig into it. For others, will reply your later. Regards Dong Aisheng diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 5d68e41..bce93c3 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -820,8 +820,12 @@ int __init mx28_clocks_init(void) * uses the other saif's BITCLK&LRCLK but it still needs a basic * clock which should be fast enough for the internal logic. */ + clk_prepare_enable(&saif0_clk); + clk_prepare_enable(&saif1_clk); clk_set_rate(&saif0_clk, 24000000); clk_set_rate(&saif1_clk, 24000000); The reason is that the clk_enable function becomes 'nops' after commit: 6abda3e ARM: mxs: select HAVE_CLK_PREPARE for clock which could cause clock not to be enabled properly. You can give a quick try.