Patchwork [v2] openpic: Added BRR1 register

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Submitter Bharat Bhushan
Date July 17, 2012, 6:30 a.m.
Message ID <1342506610-16705-1-git-send-email-Bharat.Bhushan@freescale.com>
Download mbox | patch
Permalink /patch/171341/
State New
Headers show

Comments

Bharat Bhushan - July 17, 2012, 6:30 a.m.
Linux mpic driver uses (changes may be in pipeline to get upstreamed soon)
BRR1. This patch adds the support to emulate readonly BRR1.

Currently QEMU does not fully emulate any version on MPIC, so the MPIC
Major number and Minor number are set to 0.

Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
 hw/openpic.c |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)
Alexander Graf - July 17, 2012, 8:36 a.m.
On 17.07.2012, at 08:30, Bharat Bhushan wrote:

> Linux mpic driver uses (changes may be in pipeline to get upstreamed soon)
> BRR1. This patch adds the support to emulate readonly BRR1.
> 
> Currently QEMU does not fully emulate any version on MPIC, so the MPIC
> Major number and Minor number are set to 0.

Hrm, I can't seem to find any mentioning of this register in the CPC945 spec for example.

> 
> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> ---
> hw/openpic.c |   16 ++++++++++++++++
> 1 files changed, 16 insertions(+), 0 deletions(-)
> 
> diff --git a/hw/openpic.c b/hw/openpic.c
> index 58ef871..aad2ee9 100644
> --- a/hw/openpic.c
> +++ b/hw/openpic.c
> @@ -130,6 +130,16 @@ enum {
> #define MPIC_CPU_REG_START        0x20000
> #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
> 
> +/*
> + * Block Revision Register1 (BRR1): QEMU does not fully emulate
> + * any version on MPIC. So to start with, set the IP version to 0.
> + */
> +#define BRR1_IPID 0x00400000 /* IP-block ID */

Does this mean "FSL"?


Alex

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Bharat Bhushan - July 17, 2012, 9:10 a.m.
> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Tuesday, July 17, 2012 2:06 PM
> To: Bhushan Bharat-R65777
> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org; Bhushan Bharat-R65777
> Subject: Re: [PATCH v2] openpic: Added BRR1 register
> 
> 
> On 17.07.2012, at 08:30, Bharat Bhushan wrote:
> 
> > Linux mpic driver uses (changes may be in pipeline to get upstreamed
> > soon) BRR1. This patch adds the support to emulate readonly BRR1.
> >
> > Currently QEMU does not fully emulate any version on MPIC, so the MPIC
> > Major number and Minor number are set to 0.
> 
> Hrm, I can't seem to find any mentioning of this register in the CPC945 spec for
> example.

This means that BRR1 register is FSL specific. Any suggestion on how to add FSL specific in openpic?

> 
> >
> > Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> > ---
> > hw/openpic.c |   16 ++++++++++++++++
> > 1 files changed, 16 insertions(+), 0 deletions(-)
> >
> > diff --git a/hw/openpic.c b/hw/openpic.c index 58ef871..aad2ee9 100644
> > --- a/hw/openpic.c
> > +++ b/hw/openpic.c
> > @@ -130,6 +130,16 @@ enum {
> > #define MPIC_CPU_REG_START        0x20000
> > #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
> >
> > +/*
> > + * Block Revision Register1 (BRR1): QEMU does not fully emulate
> > + * any version on MPIC. So to start with, set the IP version to 0.
> > + */
> > +#define BRR1_IPID 0x00400000 /* IP-block ID */
> 
> Does this mean "FSL"?

Yes, the value is FSL specific.

Thanks
-Bharat

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Alexander Graf - July 17, 2012, 9:18 a.m.
On 17.07.2012, at 11:10, Bhushan Bharat-R65777 wrote:

> 
> 
>> -----Original Message-----
>> From: Alexander Graf [mailto:agraf@suse.de]
>> Sent: Tuesday, July 17, 2012 2:06 PM
>> To: Bhushan Bharat-R65777
>> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org; Bhushan Bharat-R65777
>> Subject: Re: [PATCH v2] openpic: Added BRR1 register
>> 
>> 
>> On 17.07.2012, at 08:30, Bharat Bhushan wrote:
>> 
>>> Linux mpic driver uses (changes may be in pipeline to get upstreamed
>>> soon) BRR1. This patch adds the support to emulate readonly BRR1.
>>> 
>>> Currently QEMU does not fully emulate any version on MPIC, so the MPIC
>>> Major number and Minor number are set to 0.
>> 
>> Hrm, I can't seem to find any mentioning of this register in the CPC945 spec for
>> example.
> 
> This means that BRR1 register is FSL specific. Any suggestion on how to add FSL specific in openpic?

I'd say for now just declare it as such in the comment. We seriously need to refactor the whole code to adapt to different MPIC variants.

> 
>> 
>>> 
>>> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
>>> ---
>>> hw/openpic.c |   16 ++++++++++++++++
>>> 1 files changed, 16 insertions(+), 0 deletions(-)
>>> 
>>> diff --git a/hw/openpic.c b/hw/openpic.c index 58ef871..aad2ee9 100644
>>> --- a/hw/openpic.c
>>> +++ b/hw/openpic.c
>>> @@ -130,6 +130,16 @@ enum {
>>> #define MPIC_CPU_REG_START        0x20000
>>> #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
>>> 
>>> +/*
>>> + * Block Revision Register1 (BRR1): QEMU does not fully emulate
>>> + * any version on MPIC. So to start with, set the IP version to 0.
>>> + */
>>> +#define BRR1_IPID 0x00400000 /* IP-block ID */
>> 
>> Does this mean "FSL"?
> 
> Yes, the value is FSL specific.

Well, IP-block ID sounds like it's trying to tell me something. I couldn't find the semantics of what 0x400000 means. I assume it means "Freescale", which would indicate that the register isn't FSL specific. But I couldn't find it anywhere.


Alex

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Bharat Bhushan - July 17, 2012, 9:27 a.m.
> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Tuesday, July 17, 2012 2:48 PM
> To: Bhushan Bharat-R65777
> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
> Subject: Re: [PATCH v2] openpic: Added BRR1 register
> 
> 
> On 17.07.2012, at 11:10, Bhushan Bharat-R65777 wrote:
> 
> >
> >
> >> -----Original Message-----
> >> From: Alexander Graf [mailto:agraf@suse.de]
> >> Sent: Tuesday, July 17, 2012 2:06 PM
> >> To: Bhushan Bharat-R65777
> >> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org; Bhushan
> >> Bharat-R65777
> >> Subject: Re: [PATCH v2] openpic: Added BRR1 register
> >>
> >>
> >> On 17.07.2012, at 08:30, Bharat Bhushan wrote:
> >>
> >>> Linux mpic driver uses (changes may be in pipeline to get upstreamed
> >>> soon) BRR1. This patch adds the support to emulate readonly BRR1.
> >>>
> >>> Currently QEMU does not fully emulate any version on MPIC, so the
> >>> MPIC Major number and Minor number are set to 0.
> >>
> >> Hrm, I can't seem to find any mentioning of this register in the
> >> CPC945 spec for example.
> >
> > This means that BRR1 register is FSL specific. Any suggestion on how to add
> FSL specific in openpic?
> 
> I'd say for now just declare it as such in the comment. We seriously need to
> refactor the whole code to adapt to different MPIC variants.

Different MPIC variants or different OPENPIC variants?

> 
> >
> >>
> >>>
> >>> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> >>> ---
> >>> hw/openpic.c |   16 ++++++++++++++++
> >>> 1 files changed, 16 insertions(+), 0 deletions(-)
> >>>
> >>> diff --git a/hw/openpic.c b/hw/openpic.c index 58ef871..aad2ee9
> >>> 100644
> >>> --- a/hw/openpic.c
> >>> +++ b/hw/openpic.c
> >>> @@ -130,6 +130,16 @@ enum {
> >>> #define MPIC_CPU_REG_START        0x20000
> >>> #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
> >>>
> >>> +/*
> >>> + * Block Revision Register1 (BRR1): QEMU does not fully emulate
> >>> + * any version on MPIC. So to start with, set the IP version to 0.
> >>> + */
> >>> +#define BRR1_IPID 0x00400000 /* IP-block ID */
> >>
> >> Does this mean "FSL"?
> >
> > Yes, the value is FSL specific.
> 
> Well, IP-block ID sounds like it's trying to tell me something. I couldn't find
> the semantics of what 0x400000 means. I assume it means "Freescale", which would
> indicate that the register isn't FSL specific. But I couldn't find it anywhere.

IP-Block ID: it is 16 bit numeric values assigned to Hardware IPs in FSL. A specific ID means a specific IP (0x0040 - MPIC).
Probably I could have better defined this is (0x0040 << 16) with a comment.
8 bit is IP major number, 8 bit IP minor number. So this makes a 32 bit BRR1 register.

So for now adding a comment that BRR1 is FSL specific register and leave the value as is ok?

Thanks
-Bharat
> 
> 
> Alex
> 


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Alexander Graf - July 17, 2012, 9:30 a.m.
On 17.07.2012, at 11:27, Bhushan Bharat-R65777 wrote:

> 
> 
>> -----Original Message-----
>> From: Alexander Graf [mailto:agraf@suse.de]
>> Sent: Tuesday, July 17, 2012 2:48 PM
>> To: Bhushan Bharat-R65777
>> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
>> Subject: Re: [PATCH v2] openpic: Added BRR1 register
>> 
>> 
>> On 17.07.2012, at 11:10, Bhushan Bharat-R65777 wrote:
>> 
>>> 
>>> 
>>>> -----Original Message-----
>>>> From: Alexander Graf [mailto:agraf@suse.de]
>>>> Sent: Tuesday, July 17, 2012 2:06 PM
>>>> To: Bhushan Bharat-R65777
>>>> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org; Bhushan
>>>> Bharat-R65777
>>>> Subject: Re: [PATCH v2] openpic: Added BRR1 register
>>>> 
>>>> 
>>>> On 17.07.2012, at 08:30, Bharat Bhushan wrote:
>>>> 
>>>>> Linux mpic driver uses (changes may be in pipeline to get upstreamed
>>>>> soon) BRR1. This patch adds the support to emulate readonly BRR1.
>>>>> 
>>>>> Currently QEMU does not fully emulate any version on MPIC, so the
>>>>> MPIC Major number and Minor number are set to 0.
>>>> 
>>>> Hrm, I can't seem to find any mentioning of this register in the
>>>> CPC945 spec for example.
>>> 
>>> This means that BRR1 register is FSL specific. Any suggestion on how to add
>> FSL specific in openpic?
>> 
>> I'd say for now just declare it as such in the comment. We seriously need to
>> refactor the whole code to adapt to different MPIC variants.
> 
> Different MPIC variants or different OPENPIC variants?

Both :)

> 
>> 
>>> 
>>>> 
>>>>> 
>>>>> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
>>>>> ---
>>>>> hw/openpic.c |   16 ++++++++++++++++
>>>>> 1 files changed, 16 insertions(+), 0 deletions(-)
>>>>> 
>>>>> diff --git a/hw/openpic.c b/hw/openpic.c index 58ef871..aad2ee9
>>>>> 100644
>>>>> --- a/hw/openpic.c
>>>>> +++ b/hw/openpic.c
>>>>> @@ -130,6 +130,16 @@ enum {
>>>>> #define MPIC_CPU_REG_START        0x20000
>>>>> #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
>>>>> 
>>>>> +/*
>>>>> + * Block Revision Register1 (BRR1): QEMU does not fully emulate
>>>>> + * any version on MPIC. So to start with, set the IP version to 0.
>>>>> + */
>>>>> +#define BRR1_IPID 0x00400000 /* IP-block ID */
>>>> 
>>>> Does this mean "FSL"?
>>> 
>>> Yes, the value is FSL specific.
>> 
>> Well, IP-block ID sounds like it's trying to tell me something. I couldn't find
>> the semantics of what 0x400000 means. I assume it means "Freescale", which would
>> indicate that the register isn't FSL specific. But I couldn't find it anywhere.
> 
> IP-Block ID: it is 16 bit numeric values assigned to Hardware IPs in FSL. A specific ID means a specific IP (0x0040 - MPIC).
> Probably I could have better defined this is (0x0040 << 16) with a comment.
> 8 bit is IP major number, 8 bit IP minor number. So this makes a 32 bit BRR1 register.

Ah, ok. Then it does seem pretty FSL specific, right.

> So for now adding a comment that BRR1 is FSL specific register and leave the value as is ok?

Yup.


Alex

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Bharat Bhushan - July 17, 2012, 9:32 a.m.
> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Tuesday, July 17, 2012 3:01 PM
> To: Bhushan Bharat-R65777
> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
> Subject: Re: [PATCH v2] openpic: Added BRR1 register
> 
> 
> On 17.07.2012, at 11:27, Bhushan Bharat-R65777 wrote:
> 
> >
> >
> >> -----Original Message-----
> >> From: Alexander Graf [mailto:agraf@suse.de]
> >> Sent: Tuesday, July 17, 2012 2:48 PM
> >> To: Bhushan Bharat-R65777
> >> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
> >> Subject: Re: [PATCH v2] openpic: Added BRR1 register
> >>
> >>
> >> On 17.07.2012, at 11:10, Bhushan Bharat-R65777 wrote:
> >>
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: Alexander Graf [mailto:agraf@suse.de]
> >>>> Sent: Tuesday, July 17, 2012 2:06 PM
> >>>> To: Bhushan Bharat-R65777
> >>>> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org; Bhushan
> >>>> Bharat-R65777
> >>>> Subject: Re: [PATCH v2] openpic: Added BRR1 register
> >>>>
> >>>>
> >>>> On 17.07.2012, at 08:30, Bharat Bhushan wrote:
> >>>>
> >>>>> Linux mpic driver uses (changes may be in pipeline to get
> >>>>> upstreamed
> >>>>> soon) BRR1. This patch adds the support to emulate readonly BRR1.
> >>>>>
> >>>>> Currently QEMU does not fully emulate any version on MPIC, so the
> >>>>> MPIC Major number and Minor number are set to 0.
> >>>>
> >>>> Hrm, I can't seem to find any mentioning of this register in the
> >>>> CPC945 spec for example.
> >>>
> >>> This means that BRR1 register is FSL specific. Any suggestion on how
> >>> to add
> >> FSL specific in openpic?
> >>
> >> I'd say for now just declare it as such in the comment. We seriously
> >> need to refactor the whole code to adapt to different MPIC variants.
> >
> > Different MPIC variants or different OPENPIC variants?
> 
> Both :)

:)

> 
> >
> >>
> >>>
> >>>>
> >>>>>
> >>>>> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> >>>>> ---
> >>>>> hw/openpic.c |   16 ++++++++++++++++
> >>>>> 1 files changed, 16 insertions(+), 0 deletions(-)
> >>>>>
> >>>>> diff --git a/hw/openpic.c b/hw/openpic.c index 58ef871..aad2ee9
> >>>>> 100644
> >>>>> --- a/hw/openpic.c
> >>>>> +++ b/hw/openpic.c
> >>>>> @@ -130,6 +130,16 @@ enum {
> >>>>> #define MPIC_CPU_REG_START        0x20000
> >>>>> #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
> >>>>>
> >>>>> +/*
> >>>>> + * Block Revision Register1 (BRR1): QEMU does not fully emulate
> >>>>> + * any version on MPIC. So to start with, set the IP version to 0.
> >>>>> + */
> >>>>> +#define BRR1_IPID 0x00400000 /* IP-block ID */
> >>>>
> >>>> Does this mean "FSL"?
> >>>
> >>> Yes, the value is FSL specific.
> >>
> >> Well, IP-block ID sounds like it's trying to tell me something. I
> >> couldn't find the semantics of what 0x400000 means. I assume it means
> >> "Freescale", which would indicate that the register isn't FSL specific. But I
> couldn't find it anywhere.
> >
> > IP-Block ID: it is 16 bit numeric values assigned to Hardware IPs in FSL. A
> specific ID means a specific IP (0x0040 - MPIC).
> > Probably I could have better defined this is (0x0040 << 16) with a comment.
> > 8 bit is IP major number, 8 bit IP minor number. So this makes a 32 bit BRR1
> register.
> 
> Ah, ok. Then it does seem pretty FSL specific, right.

Yes.

-Bharat

> 
> > So for now adding a comment that BRR1 is FSL specific register and leave the
> value as is ok?
> 
> Yup.
> 
> 
> Alex
> 


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Patch

diff --git a/hw/openpic.c b/hw/openpic.c
index 58ef871..aad2ee9 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -130,6 +130,16 @@  enum {
 #define MPIC_CPU_REG_START        0x20000
 #define MPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
 
+/*
+ * Block Revision Register1 (BRR1): QEMU does not fully emulate
+ * any version on MPIC. So to start with, set the IP version to 0.
+ */
+#define BRR1_IPID 0x00400000 /* IP-block ID */
+#define BRR1_IPMJ 0x00000000 /* IP major number */
+#define BRR1_IPMN 0x00000000 /* IP minor number */
+
+
+
 enum mpic_ide_bits {
     IDR_EP     = 31,
     IDR_CI0     = 30,
@@ -595,6 +605,8 @@  static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
     if (addr & 0xF)
         return;
     switch (addr) {
+    case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
+        break;
     case 0x40:
     case 0x50:
     case 0x60:
@@ -671,6 +683,7 @@  static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
     case 0x1090: /* PINT */
         retval = 0x00000000;
         break;
+    case 0x00: /* Block Revision Register1 (BRR1) */
     case 0x40:
     case 0x50:
     case 0x60:
@@ -893,6 +906,9 @@  static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
     dst = &opp->dst[idx];
     addr &= 0xFF0;
     switch (addr) {
+    case 0x00: /* Block Revision Register1 (BRR1) */
+        retval = BRR1_IPID | BRR1_IPMJ | BRR1_IPMN;
+        break;
     case 0x80: /* PCTP */
         retval = dst->pctp;
         break;