From patchwork Mon Jul 16 23:02:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen Martin X-Patchwork-Id: 171285 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A6D282C013D for ; Tue, 17 Jul 2012 09:04:45 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9794B281EB; Tue, 17 Jul 2012 01:04:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id osIKLP1jxMoy; Tue, 17 Jul 2012 01:04:42 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6313D281EC; Tue, 17 Jul 2012 01:03:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4BAC0281C4 for ; Tue, 17 Jul 2012 01:03:20 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qQGEfMlJucdB for ; Tue, 17 Jul 2012 01:03:19 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from hqemgate03.nvidia.com (hqemgate03.nvidia.com [216.228.121.140]) by theia.denx.de (Postfix) with ESMTPS id 1FC61281CD for ; Tue, 17 Jul 2012 01:03:11 +0200 (CEST) Received: from hqnvupgp06.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Mon, 16 Jul 2012 16:03:41 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp06.nvidia.com (PGP Universal service); Mon, 16 Jul 2012 16:03:09 -0700 X-PGP-Universal: processed; by hqnvupgp06.nvidia.com on Mon, 16 Jul 2012 16:03:09 -0700 Received: from badger.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.264.0; Mon, 16 Jul 2012 16:03:09 -0700 From: Allen Martin To: , , , Date: Mon, 16 Jul 2012 16:02:15 -0700 Message-ID: <1342479739-7594-12-git-send-email-amartin@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342479739-7594-1-git-send-email-amartin@nvidia.com> References: <1342479739-7594-1-git-send-email-amartin@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v7 11/15] tegra20: move SDRAM param save to later in boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Move warmboot_save_sdram_params() to later in the boot sequence. This code relies on devicetree to get the address of the memory controller and with upcoming changes for SPL boot it gets called early in the boot process when devicetree is not initialized yet. Signed-off-by: Allen Martin Acked-by: Stephen Warren Tested-by: Thierry Reding --- arch/arm/cpu/tegra20-common/ap20.c | 5 ----- board/nvidia/common/board.c | 3 +++ 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c index 8b6afbc..6ff71e0 100644 --- a/arch/arm/cpu/tegra20-common/ap20.c +++ b/arch/arm/cpu/tegra20-common/ap20.c @@ -345,11 +345,6 @@ void init_pmc_scratch(void) /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ odmdata = get_odmdata(); writel(odmdata, &pmc->pmc_scratch20); - -#ifdef CONFIG_TEGRA20_LP0 - /* save Sdram params to PMC 2, 4, and 24 for WB0 */ - warmboot_save_sdram_params(); -#endif } void tegra20_start(void) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 6753f95..7ab2040 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -133,6 +133,9 @@ int board_init(void) #endif #ifdef CONFIG_TEGRA20_LP0 + /* save Sdram params to PMC 2, 4, and 24 for WB0 */ + warmboot_save_sdram_params(); + /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif