From patchwork Fri Jul 13 11:07:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guan Xuetao X-Patchwork-Id: 170863 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BCDD52C0362 for ; Fri, 13 Jul 2012 21:25:18 +1000 (EST) Received: from localhost ([::1]:60916 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Spdzm-0007rj-UH for incoming@patchwork.ozlabs.org; Fri, 13 Jul 2012 07:25:14 -0400 Received: from eggs.gnu.org ([208.118.235.92]:46332) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpdsR-0001lO-Q6 for qemu-devel@nongnu.org; Fri, 13 Jul 2012 07:17:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SpdsL-0006C4-MF for qemu-devel@nongnu.org; Fri, 13 Jul 2012 07:17:39 -0400 Received: from mprc.pku.edu.cn ([162.105.203.9]:34871) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpdsK-0006Br-Pj for qemu-devel@nongnu.org; Fri, 13 Jul 2012 07:17:33 -0400 Received: from linuxdev-32 ([162.105.203.8]) by mprc.pku.edu.cn (8.13.8/8.13.8) with ESMTP id q6DBxZS4023847; Fri, 13 Jul 2012 19:59:35 +0800 Received: by linuxdev-32 (Postfix, from userid 1000) id 704301460526; Fri, 13 Jul 2012 19:07:53 +0800 (CST) From: Guan Xuetao To: qemu-devel@nongnu.org Date: Fri, 13 Jul 2012 19:07:41 +0800 Message-Id: <4fa8efb298c6525866418068af5cf9b6f34c9460.1342176596.git.gxt@mprc.pku.edu.cn> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 162.105.203.9 Cc: blauwirbel@gmail.com, Guan Xuetao , afaerber@suse.de, chenwj@iis.sinica.edu.tw Subject: [Qemu-devel] [PATCHv4 06/14] unicore32-softmmu: Make sure that kernel can access user space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org As a matter of course, we need to access user space in kernel code, so we need to correct load/store decoders to indicate correct memory region. Signed-off-by: Guan Xuetao --- target-unicore32/translate.c | 36 ++++++++++++++++++++++++++---------- 1 files changed, 26 insertions(+), 10 deletions(-) diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index e37d5be..5ee3a59 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -33,9 +33,16 @@ typedef struct DisasContext { int condlabel; struct TranslationBlock *tb; int singlestep_enabled; +#ifndef CONFIG_USER_ONLY + int user; +#endif } DisasContext; -#define IS_USER(s) 1 +#ifndef CONFIG_USER_ONLY +#define IS_USER(s) (s->user) +#else +#define IS_USER(s) 1 +#endif /* These instructions trap after executing, so defer them until after the conditional executions state has been updated. */ @@ -1554,12 +1561,12 @@ static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store I_offset and R_offset */ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - unsigned int i; + unsigned int mmu_idx; TCGv tmp; TCGv tmp2; tmp2 = load_reg(s, UCOP_REG_N); - i = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W)); + mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W)); /* immediate */ if (UCOP_SET_P) { @@ -1569,17 +1576,17 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn) if (UCOP_SET_L) { /* load */ if (UCOP_SET_B) { - tmp = gen_ld8u(tmp2, i); + tmp = gen_ld8u(tmp2, mmu_idx); } else { - tmp = gen_ld32(tmp2, i); + tmp = gen_ld32(tmp2, mmu_idx); } } else { /* store */ tmp = load_reg(s, UCOP_REG_D); if (UCOP_SET_B) { - gen_st8(tmp, tmp2, i); + gen_st8(tmp, tmp2, mmu_idx); } else { - gen_st32(tmp, tmp2, i); + gen_st32(tmp, tmp2, mmu_idx); } } if (!UCOP_SET_P) { @@ -1682,7 +1689,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store multiple words */ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { - unsigned int val, i; + unsigned int val, i, mmu_idx; int j, n, reg, user, loaded_base; TCGv tmp; TCGv tmp2; @@ -1703,6 +1710,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) } } + mmu_idx = (IS_USER(s) || (!UCOP_SET_P && UCOP_SET_W)); addr = load_reg(s, UCOP_REG_N); /* compute total size */ @@ -1747,7 +1755,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) } if (UCOP_SET(i)) { if (UCOP_SET_L) { /* load */ - tmp = gen_ld32(addr, IS_USER(s)); + tmp = gen_ld32(addr, mmu_idx); if (reg == 31) { gen_bx(s, tmp); } else if (user) { @@ -1775,7 +1783,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) } else { tmp = load_reg(s, reg); } - gen_st32(tmp, addr, IS_USER(s)); + gen_st32(tmp, addr, mmu_idx); } j++; /* no need to add after the last transfer */ @@ -1964,6 +1972,14 @@ static inline void gen_intermediate_code_internal(CPUUniCore32State *env, max_insns = CF_COUNT_MASK; } +#ifndef CONFIG_USER_ONLY + if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) { + dc->user = 1; + } else { + dc->user = 0; + } +#endif + gen_icount_start(); do { if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {