From patchwork Fri Jul 13 04:34:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 170780 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 64ACC2C0331 for ; Fri, 13 Jul 2012 14:36:48 +1000 (EST) Received: from localhost ([::1]:44511 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpXcU-0006fR-H1 for incoming@patchwork.ozlabs.org; Fri, 13 Jul 2012 00:36:46 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56738) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpXc7-0006NV-Py for qemu-devel@nongnu.org; Fri, 13 Jul 2012 00:36:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SpXc6-0005EQ-6L for qemu-devel@nongnu.org; Fri, 13 Jul 2012 00:36:23 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:51254) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpXc6-0004pv-08 for qemu-devel@nongnu.org; Fri, 13 Jul 2012 00:36:22 -0400 Received: by mail-pb0-f45.google.com with SMTP id ro12so5077097pbb.4 for ; Thu, 12 Jul 2012 21:36:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=f3Zgj2ZhxsspenAWCGFjo2UbPXTb61EAmzuxR+8NKCU=; b=JkZG193o0ZlsjkCu2X4VUiElgaT2KtBi8tbGlJ1wtqT8v24rKiOOiZ4hMpOai8/AMH 9vbCvN5xYeVWzgzdr+OeoeGe73Ufpy/ZWbELF5TOQRFullj5urQqh2Fa6dgPdWRU76gE eXBVxPOedC/OQBJo5yr7QRHZ+F5oUgEQXzf8FrYGJPUgiYTm/g0FnrOSAZ23EAgUEZ2Y C0ZBIG/0AKZY2YYWtbe2Zolk9AaKowLevq7yKi7vDG7P0+YOTmamI1TFcRJcQWrGYK+X 6kMhdICJ+yymQYJBbMFW3KQumBWthgw6TECMW5Z/0XsTzIxN2PCrWaBAX38B+cp0YqAL vhyQ== Received: by 10.66.73.70 with SMTP id j6mr2049128pav.5.1342154181591; Thu, 12 Jul 2012 21:36:21 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id sk5sm5203558pbc.7.2012.07.12.21.36.16 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 12 Jul 2012 21:36:20 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Fri, 13 Jul 2012 12:34:58 +0800 Message-Id: <1342154108-798-6-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1342154108-798-1-git-send-email-proljc@gmail.com> References: <1342154108-798-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: afaerber@suse.de Subject: [Qemu-devel] [PATCH v9 05/15] target-or32: Add int instruction helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add OpenRISC int instruction helpers. Signed-off-by: Jia Liu --- target-openrisc/Makefile.objs | 2 +- target-openrisc/helper.h | 5 +++ target-openrisc/int_helper.c | 87 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+), 1 deletion(-) create mode 100644 target-openrisc/int_helper.c diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.objs index 52d0158..e2a3715 100644 --- a/target-openrisc/Makefile.objs +++ b/target-openrisc/Makefile.objs @@ -1,3 +1,3 @@ obj-$(CONFIG_SOFTMMU) += machine.o obj-y += cpu.o exception.o interrupt.o mmu.o translate.o -obj-y += exception_helper.o interrupt_helper.o mmu_helper.o +obj-y += exception_helper.o int_helper.o interrupt_helper.o mmu_helper.o diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h index 4e2a49f..c772951 100644 --- a/target-openrisc/helper.h +++ b/target-openrisc/helper.h @@ -22,6 +22,11 @@ /* exception */ DEF_HELPER_FLAGS_2(exception, 0, void, env, i32) +/* int */ +DEF_HELPER_FLAGS_1(ff1, 0, tl, tl) +DEF_HELPER_FLAGS_1(fl1, 0, tl, tl) +DEF_HELPER_FLAGS_3(mul32, 0, tl, env, tl, tl) + /* interrupt */ DEF_HELPER_FLAGS_1(rfe, 0, void, env) diff --git a/target-openrisc/int_helper.c b/target-openrisc/int_helper.c new file mode 100644 index 0000000..45a9bfd --- /dev/null +++ b/target-openrisc/int_helper.c @@ -0,0 +1,87 @@ +/* + * OpenRISC int helper routines + * + * Copyright (c) 2011-2012 Jia Liu + * Feng Gao + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "cpu.h" +#include "helper.h" +#include "exception.h" + +target_ulong HELPER(ff1)(target_ulong x) +{ + target_ulong n = 0; + + if (x == 0) { + return 0; + } + + for (n = 32; x; n--) { + x <<= 1; + } + return n+1; +} + +target_ulong HELPER(fl1)(target_ulong x) +{ + target_ulong n = 0; + + if (x == 0) { + return 0; + } + + for (n = 0; x; n++) { + x >>= 1; + } + return n; +} + +target_ulong HELPER(mul32)(CPUOpenRISCState *env, + target_ulong ra, target_ulong rb) +{ + uint64_t result; + target_ulong high, cy; + + OpenRISCCPU *cpu = OPENRISC_CPU(ENV_GET_CPU(env)); + + result = ra * rb; + /* regisiers in or32 is 32bit, so 32 is NOT a magic number. + or64 is not handled in this function, and not implement yet, + TARGET_LONG_BITS for or64 is 64, it will break this function, + so, we didn't use TARGET_LONG_BITS here. */ + high = result >> 32; + cy = result >> (32 - 1); + + if ((cy & 0x1) == 0x0) { + if (high == 0x0) { + return result; + } + } + + if ((cy & 0x1) == 0x1) { + if (high == 0xffffffff) { + return result; + } + } + + cpu->env.sr |= (SR_OV | SR_CY); + if (cpu->env.sr & SR_OVE) { + raise_exception(cpu, EXCP_RANGE); + } + + return result; +}