From patchwork Thu Jul 12 16:54:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maksim E. Kozlov" X-Patchwork-Id: 170734 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9B5FD2C02C5 for ; Fri, 13 Jul 2012 03:29:57 +1000 (EST) Received: from localhost ([::1]:37091 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpMg5-0000Qf-UL for incoming@patchwork.ozlabs.org; Thu, 12 Jul 2012 12:55:45 -0400 Received: from eggs.gnu.org ([208.118.235.92]:49994) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpMfc-0007g1-1I for qemu-devel@nongnu.org; Thu, 12 Jul 2012 12:55:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SpMfP-00080j-WC for qemu-devel@nongnu.org; Thu, 12 Jul 2012 12:55:15 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:10189) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SpMfP-0007zm-QO for qemu-devel@nongnu.org; Thu, 12 Jul 2012 12:55:03 -0400 Received: from eusync3.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M7200D7X4CJNT00@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Thu, 12 Jul 2012 17:55:31 +0100 (BST) Received: from felix.rnd.samsung.ru ([106.109.9.187]) by eusync3.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0M72009E74AVG690@eusync3.samsung.com> for qemu-devel@nongnu.org; Thu, 12 Jul 2012 17:55:02 +0100 (BST) From: Maksim Kozlov To: qemu-devel@nongnu.org Date: Thu, 12 Jul 2012 20:54:28 +0400 Message-id: <1342112068-23345-5-git-send-email-m.kozlov@samsung.com> X-Mailer: git-send-email 1.7.5.4 In-reply-to: <1342112068-23345-1-git-send-email-m.kozlov@samsung.com> References: <1342112068-23345-1-git-send-email-m.kozlov@samsung.com> X-TM-AS-MML: No X-detected-operating-system: by eggs.gnu.org: Solaris 10 (1203?) X-Received-From: 210.118.77.12 Cc: peter.maydell@linaro.org, kyungmin.park@samsung.com, Maksim Kozlov , e.voevodin@samsung.com Subject: [Qemu-devel] [PATCH v2 4/4] ARM: exynos4210_pmu: Add software reset support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Maksim Kozlov --- hw/exynos4210_pmu.c | 40 +++++++++++++++++++++++++++++++++------- 1 files changed, 33 insertions(+), 7 deletions(-) diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c index 7f09c79..96588d9 100644 --- a/hw/exynos4210_pmu.c +++ b/hw/exynos4210_pmu.c @@ -18,13 +18,8 @@ * with this program; if not, see . */ -/* - * This model implements PMU registers just as a bulk of memory. Currently, - * the only reason this device exists is that secondary CPU boot loader - * uses PMU INFORM5 register as a holding pen. - */ - #include "sysbus.h" +#include "sysemu.h" #ifndef DEBUG_PMU #define DEBUG_PMU 0 @@ -230,6 +225,8 @@ #define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c +#define SWRESET_SYSTEM_MASK 0x00000001 + typedef struct Exynos4210PmuReg { const char *name; /* for debug only */ uint32_t offset; @@ -458,7 +455,17 @@ static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset, PRINT_DEBUG_EXTEND("%s [0x%04x] <- 0x%04x\n", exynos4210_pmu_regs[index].name, (uint32_t)offset, (uint32_t)val); - s->reg[index] = val; + switch (offset) { + case SWRESET: + if (val & SWRESET_SYSTEM_MASK) { + s->reg[index] = val; + qemu_system_reset_request(); + } + break; + default: + s->reg[index] = val; + break; + } } static const MemoryRegionOps exynos4210_pmu_ops = { @@ -477,9 +484,28 @@ static void exynos4210_pmu_reset(DeviceState *dev) Exynos4210PmuState *s = container_of(dev, Exynos4210PmuState, busdev.qdev); unsigned i; + uint32_t index = exynos4210_pmu_get_register_index(s, SWRESET); + uint32_t swreset = s->reg[index]; /* Set default values for registers */ for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { + if (swreset) { + switch (exynos4210_pmu_regs[i].offset) { + case INFORM0: + case INFORM1: + case INFORM2: + case INFORM3: + case INFORM4: + case INFORM5: + case INFORM6: + case INFORM7: + case PS_HOLD_CONTROL: + /* keep these registers during SW reset */ + continue; + default: + break; + } + } s->reg[i] = exynos4210_pmu_regs[i].reset_value; } }