Patchwork openpic: Added BRR1 register

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Submitter Bharat Bhushan
Date July 12, 2012, 11:07 a.m.
Message ID <1342091277-7122-1-git-send-email-Bharat.Bhushan@freescale.com>
Download mbox | patch
Permalink /patch/170639/
State New
Headers show

Comments

Bharat Bhushan - July 12, 2012, 11:07 a.m.
Linux mpic driver uses (changes may be in pipeline to get upstreamed soon)
BRR1. This patch adds the support to emulate readonly BRR1.

Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
 hw/openpic.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)
Alexander Graf - July 16, 2012, 2:55 p.m.
On 07/12/2012 01:07 PM, Bharat Bhushan wrote:
> Linux mpic driver uses (changes may be in pipeline to get upstreamed soon)
> BRR1. This patch adds the support to emulate readonly BRR1.
>
> Signed-off-by: Bharat Bhushan<bharat.bhushan@freescale.com>
> ---
>   hw/openpic.c |    6 ++++++
>   1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/hw/openpic.c b/hw/openpic.c
> index 58ef871..244155b 100644
> --- a/hw/openpic.c
> +++ b/hw/openpic.c
> @@ -595,6 +595,8 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
>       if (addr&  0xF)
>           return;
>       switch (addr) {
> +    case 0x00: /* BRR1 Readonly */
> +        break;
>       case 0x40:
>       case 0x50:
>       case 0x60:
> @@ -671,6 +673,7 @@ static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
>       case 0x1090: /* PINT */
>           retval = 0x00000000;
>           break;
> +    case 0x00:

Add a comment saying what register this is. We really should be using 
#define's here, but it would be even worse to have it converted only 
half-way, so just stick with the comment for now.

>       case 0x40:
>       case 0x50:
>       case 0x60:
> @@ -893,6 +896,9 @@ static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
>       dst =&opp->dst[idx];
>       addr&= 0xFF0;
>       switch (addr) {
> +    case 0x00: /* BRR1 */
> +        retval = 0x00400200;

Please unmagicify this one :)


Alex

> +        break;
>       case 0x80: /* PCTP */
>           retval = dst->pctp;
>           break;

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Bharat Bhushan - July 16, 2012, 4:21 p.m.
> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Monday, July 16, 2012 8:25 PM
> To: Bhushan Bharat-R65777
> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org; Bhushan Bharat-R65777
> Subject: Re: [PATCH] openpic: Added BRR1 register
> 
> On 07/12/2012 01:07 PM, Bharat Bhushan wrote:
> > Linux mpic driver uses (changes may be in pipeline to get upstreamed
> > soon) BRR1. This patch adds the support to emulate readonly BRR1.
> >
> > Signed-off-by: Bharat Bhushan<bharat.bhushan@freescale.com>
> > ---
> >   hw/openpic.c |    6 ++++++
> >   1 files changed, 6 insertions(+), 0 deletions(-)
> >
> > diff --git a/hw/openpic.c b/hw/openpic.c index 58ef871..244155b 100644
> > --- a/hw/openpic.c
> > +++ b/hw/openpic.c
> > @@ -595,6 +595,8 @@ static void openpic_gbl_write (void *opaque,
> target_phys_addr_t addr, uint32_t v
> >       if (addr&  0xF)
> >           return;
> >       switch (addr) {
> > +    case 0x00: /* BRR1 Readonly */
> > +        break;
> >       case 0x40:
> >       case 0x50:
> >       case 0x60:
> > @@ -671,6 +673,7 @@ static uint32_t openpic_gbl_read (void *opaque,
> target_phys_addr_t addr)
> >       case 0x1090: /* PINT */
> >           retval = 0x00000000;
> >           break;
> > +    case 0x00:
> 
> Add a comment saying what register this is. We really should be using #define's
> here, but it would be even worse to have it converted only half-way, so just
> stick with the comment for now.

Ok, I have added on write but forgot here.

> 
> >       case 0x40:
> >       case 0x50:
> >       case 0x60:
> > @@ -893,6 +896,9 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
> target_phys_addr_t addr,
> >       dst =&opp->dst[idx];
> >       addr&= 0xFF0;
> >       switch (addr) {
> > +    case 0x00: /* BRR1 */
> > +        retval = 0x00400200;
> 
> Please unmagicify this one :)

/* BRR1 ( Block revision register ) */

#define IPID 0x00400000 /* IP-block ID */
#define IPMJ 0x00000200 /* IP major number */
#define IPMN 0x00000200 /* IP minor number */

        case 0x00: /* BRR1 */
            retval = IPID | IPMJ | IPMN;

Dose this look ok?

Thanks
-Bharat

> 
>
> Alex
> 
> > +        break;
> >       case 0x80: /* PCTP */
> >           retval = dst->pctp;
> >           break;
> 


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Alexander Graf - July 16, 2012, 4:26 p.m.
On 16.07.2012, at 18:21, Bhushan Bharat-R65777 <R65777@freescale.com> wrote:

> 
> 
>> -----Original Message-----
>> From: Alexander Graf [mailto:agraf@suse.de]
>> Sent: Monday, July 16, 2012 8:25 PM
>> To: Bhushan Bharat-R65777
>> Cc: qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org; Bhushan Bharat-R65777
>> Subject: Re: [PATCH] openpic: Added BRR1 register
>> 
>> On 07/12/2012 01:07 PM, Bharat Bhushan wrote:
>>> Linux mpic driver uses (changes may be in pipeline to get upstreamed
>>> soon) BRR1. This patch adds the support to emulate readonly BRR1.
>>> 
>>> Signed-off-by: Bharat Bhushan<bharat.bhushan@freescale.com>
>>> ---
>>>  hw/openpic.c |    6 ++++++
>>>  1 files changed, 6 insertions(+), 0 deletions(-)
>>> 
>>> diff --git a/hw/openpic.c b/hw/openpic.c index 58ef871..244155b 100644
>>> --- a/hw/openpic.c
>>> +++ b/hw/openpic.c
>>> @@ -595,6 +595,8 @@ static void openpic_gbl_write (void *opaque,
>> target_phys_addr_t addr, uint32_t v
>>>      if (addr&  0xF)
>>>          return;
>>>      switch (addr) {
>>> +    case 0x00: /* BRR1 Readonly */
>>> +        break;
>>>      case 0x40:
>>>      case 0x50:
>>>      case 0x60:
>>> @@ -671,6 +673,7 @@ static uint32_t openpic_gbl_read (void *opaque,
>> target_phys_addr_t addr)
>>>      case 0x1090: /* PINT */
>>>          retval = 0x00000000;
>>>          break;
>>> +    case 0x00:
>> 
>> Add a comment saying what register this is. We really should be using #define's
>> here, but it would be even worse to have it converted only half-way, so just
>> stick with the comment for now.
> 
> Ok, I have added on write but forgot here.
> 
>> 
>>>      case 0x40:
>>>      case 0x50:
>>>      case 0x60:
>>> @@ -893,6 +896,9 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
>> target_phys_addr_t addr,
>>>      dst =&opp->dst[idx];
>>>      addr&= 0xFF0;
>>>      switch (addr) {
>>> +    case 0x00: /* BRR1 */
>>> +        retval = 0x00400200;
>> 
>> Please unmagicify this one :)
> 
> /* BRR1 ( Block revision register ) */
> 
> #define IPID 0x00400000 /* IP-block ID */
> #define IPMJ 0x00000200 /* IP major number */
> #define IPMN 0x00000200 /* IP minor number */
> 
>        case 0x00: /* BRR1 */
>            retval = IPID | IPMJ | IPMN;
> 
> Dose this look ok?

Yup :)

Alex

> 
> Thanks
> -Bharat
> 
>> 
>> 
>> Alex
>> 
>>> +        break;
>>>      case 0x80: /* PCTP */
>>>          retval = dst->pctp;
>>>          break;
>> 
> 
> 
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Scott Wood - July 16, 2012, 5:03 p.m.
On 07/16/2012 11:21 AM, Bhushan Bharat-R65777 wrote:
>>> +    case 0x00: /* BRR1 */
>>> +        retval = 0x00400200;
>>
>> Please unmagicify this one :)
> 
> /* BRR1 ( Block revision register ) */
> 
> #define IPID 0x00400000 /* IP-block ID */
> #define IPMJ 0x00000200 /* IP major number */
> #define IPMN 0x00000200 /* IP minor number */

IPMN looks wrong.

-Scott

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Scott Wood - July 16, 2012, 5:11 p.m.
On 07/16/2012 12:09 PM, Bhushan Bharat-R65777 wrote:
> 
> 
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Monday, July 16, 2012 10:34 PM
>> To: Bhushan Bharat-R65777
>> Cc: Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
>> Subject: Re: [PATCH] openpic: Added BRR1 register
>>
>> On 07/16/2012 11:21 AM, Bhushan Bharat-R65777 wrote:
>>>>> +    case 0x00: /* BRR1 */
>>>>> +        retval = 0x00400200;
>>>>
>>>> Please unmagicify this one :)
>>>
>>> /* BRR1 ( Block revision register ) */
>>>
>>> #define IPID 0x00400000 /* IP-block ID */ #define IPMJ 0x00000200 /*
>>> IP major number */ #define IPMN 0x00000200 /* IP minor number */
>>
>> IPMN looks wrong.
> 
> Opps : copy paste error here :)
> 
> Btw, I am not aware of all MPIC IP versions, differences in them and what is the latest/best version this emulated code supports. I drive this value from mpc8544 Reference Manual.
> 
> I requested Alex to suggest the most updated version.

QEMU does not have a complete implementation of any version of the FSL MPIC.

-Scott

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Yoder Stuart-B08248 - July 16, 2012, 7:29 p.m.
> -----Original Message-----

> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-owner@vger.kernel.org] On Behalf Of Scott Wood

> Sent: Monday, July 16, 2012 12:12 PM

> To: Bhushan Bharat-R65777

> Cc: Wood Scott-B07421; Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org

> Subject: Re: [PATCH] openpic: Added BRR1 register

> 

> On 07/16/2012 12:09 PM, Bhushan Bharat-R65777 wrote:

> >

> >

> >> -----Original Message-----

> >> From: Wood Scott-B07421

> >> Sent: Monday, July 16, 2012 10:34 PM

> >> To: Bhushan Bharat-R65777

> >> Cc: Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org

> >> Subject: Re: [PATCH] openpic: Added BRR1 register

> >>

> >> On 07/16/2012 11:21 AM, Bhushan Bharat-R65777 wrote:

> >>>>> +    case 0x00: /* BRR1 */

> >>>>> +        retval = 0x00400200;

> >>>>

> >>>> Please unmagicify this one :)

> >>>

> >>> /* BRR1 ( Block revision register ) */

> >>>

> >>> #define IPID 0x00400000 /* IP-block ID */ #define IPMJ 0x00000200 /*

> >>> IP major number */ #define IPMN 0x00000200 /* IP minor number */

> >>

> >> IPMN looks wrong.

> >

> > Opps : copy paste error here :)

> >

> > Btw, I am not aware of all MPIC IP versions, differences in them and what is the latest/best version

> this emulated code supports. I drive this value from mpc8544 Reference Manual.

> >

> > I requested Alex to suggest the most updated version.

> 

> QEMU does not have a complete implementation of any version of the FSL MPIC.


So what revision numbers should we use?

Stuart
Scott Wood - July 16, 2012, 7:32 p.m.
On 07/16/2012 02:29 PM, Yoder Stuart-B08248 wrote:
> 
> 
>> -----Original Message-----
>> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-owner@vger.kernel.org] On Behalf Of Scott Wood
>> Sent: Monday, July 16, 2012 12:12 PM
>> To: Bhushan Bharat-R65777
>> Cc: Wood Scott-B07421; Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
>> Subject: Re: [PATCH] openpic: Added BRR1 register
>>
>> On 07/16/2012 12:09 PM, Bhushan Bharat-R65777 wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Wood Scott-B07421
>>>> Sent: Monday, July 16, 2012 10:34 PM
>>>> To: Bhushan Bharat-R65777
>>>> Cc: Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
>>>> Subject: Re: [PATCH] openpic: Added BRR1 register
>>>>
>>>> On 07/16/2012 11:21 AM, Bhushan Bharat-R65777 wrote:
>>>>>>> +    case 0x00: /* BRR1 */
>>>>>>> +        retval = 0x00400200;
>>>>>>
>>>>>> Please unmagicify this one :)
>>>>>
>>>>> /* BRR1 ( Block revision register ) */
>>>>>
>>>>> #define IPID 0x00400000 /* IP-block ID */ #define IPMJ 0x00000200 /*
>>>>> IP major number */ #define IPMN 0x00000200 /* IP minor number */
>>>>
>>>> IPMN looks wrong.
>>>
>>> Opps : copy paste error here :)
>>>
>>> Btw, I am not aware of all MPIC IP versions, differences in them and what is the latest/best version
>> this emulated code supports. I drive this value from mpc8544 Reference Manual.
>>>
>>> I requested Alex to suggest the most updated version.
>>
>> QEMU does not have a complete implementation of any version of the FSL MPIC.
> 
> So what revision numbers should we use?

How about 0.0 for now?

-Scott

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Alexander Graf - July 16, 2012, 8:09 p.m.
On 16.07.2012, at 21:32, Scott Wood wrote:

> On 07/16/2012 02:29 PM, Yoder Stuart-B08248 wrote:
>> 
>> 
>>> -----Original Message-----
>>> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-owner@vger.kernel.org] On Behalf Of Scott Wood
>>> Sent: Monday, July 16, 2012 12:12 PM
>>> To: Bhushan Bharat-R65777
>>> Cc: Wood Scott-B07421; Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
>>> Subject: Re: [PATCH] openpic: Added BRR1 register
>>> 
>>> On 07/16/2012 12:09 PM, Bhushan Bharat-R65777 wrote:
>>>> 
>>>> 
>>>>> -----Original Message-----
>>>>> From: Wood Scott-B07421
>>>>> Sent: Monday, July 16, 2012 10:34 PM
>>>>> To: Bhushan Bharat-R65777
>>>>> Cc: Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
>>>>> Subject: Re: [PATCH] openpic: Added BRR1 register
>>>>> 
>>>>> On 07/16/2012 11:21 AM, Bhushan Bharat-R65777 wrote:
>>>>>>>> +    case 0x00: /* BRR1 */
>>>>>>>> +        retval = 0x00400200;
>>>>>>> 
>>>>>>> Please unmagicify this one :)
>>>>>> 
>>>>>> /* BRR1 ( Block revision register ) */
>>>>>> 
>>>>>> #define IPID 0x00400000 /* IP-block ID */ #define IPMJ 0x00000200 /*
>>>>>> IP major number */ #define IPMN 0x00000200 /* IP minor number */
>>>>> 
>>>>> IPMN looks wrong.
>>>> 
>>>> Opps : copy paste error here :)
>>>> 
>>>> Btw, I am not aware of all MPIC IP versions, differences in them and what is the latest/best version
>>> this emulated code supports. I drive this value from mpc8544 Reference Manual.
>>>> 
>>>> I requested Alex to suggest the most updated version.
>>> 
>>> QEMU does not have a complete implementation of any version of the FSL MPIC.
>> 
>> So what revision numbers should we use?
> 
> How about 0.0 for now?

Would guests care (read: break)?


Alex

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Scott Wood - July 16, 2012, 9:16 p.m.
On 07/16/2012 03:09 PM, Alexander Graf wrote:
> 
> On 16.07.2012, at 21:32, Scott Wood wrote:
> 
>> On 07/16/2012 02:29 PM, Yoder Stuart-B08248 wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-owner@vger.kernel.org] On Behalf Of Scott Wood
>>>> Sent: Monday, July 16, 2012 12:12 PM
>>>> To: Bhushan Bharat-R65777
>>>> Cc: Wood Scott-B07421; Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
>>>> Subject: Re: [PATCH] openpic: Added BRR1 register
>>>>
>>>> On 07/16/2012 12:09 PM, Bhushan Bharat-R65777 wrote:
>>>>>
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Wood Scott-B07421
>>>>>> Sent: Monday, July 16, 2012 10:34 PM
>>>>>> To: Bhushan Bharat-R65777
>>>>>> Cc: Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
>>>>>> Subject: Re: [PATCH] openpic: Added BRR1 register
>>>>>>
>>>>>> On 07/16/2012 11:21 AM, Bhushan Bharat-R65777 wrote:
>>>>>>>>> +    case 0x00: /* BRR1 */
>>>>>>>>> +        retval = 0x00400200;
>>>>>>>>
>>>>>>>> Please unmagicify this one :)
>>>>>>>
>>>>>>> /* BRR1 ( Block revision register ) */
>>>>>>>
>>>>>>> #define IPID 0x00400000 /* IP-block ID */ #define IPMJ 0x00000200 /*
>>>>>>> IP major number */ #define IPMN 0x00000200 /* IP minor number */
>>>>>>
>>>>>> IPMN looks wrong.
>>>>>
>>>>> Opps : copy paste error here :)
>>>>>
>>>>> Btw, I am not aware of all MPIC IP versions, differences in them and what is the latest/best version
>>>> this emulated code supports. I drive this value from mpc8544 Reference Manual.
>>>>>
>>>>> I requested Alex to suggest the most updated version.
>>>>
>>>> QEMU does not have a complete implementation of any version of the FSL MPIC.
>>>
>>> So what revision numbers should we use?
>>
>> How about 0.0 for now?
> 
> Would guests care (read: break)?

I can't answer that question for "guests" in general.  They could just
as well break due to the missing functionality.

Linux currently does not look at the version information, though there
are a couple patches posted that do depend on it to check for certain
features.  If it sees 0.0, it won't use features that aren't there.

One thing that might break if we claim 2.0 is that there was a patch
posted over the weekend that assumes an MSI erratum on version 2.0.
This would break if we're directly assigning a non-broken MSI block to
the guest, since the rest of the MPIC is still emulated.  That said, it
wouldn't be QEMU's fault.  It's a combination that doesn't exist in real
hardware and it shouldn't be surprising that the guest might need some
fixing to accommodate it.

-Scott

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Yin Olivia-R63875 - July 17, 2012, 2:57 a.m.
FYI, MPIC version on P4080 is 0401.
#define IPMJ 0x00000400
#define IPMN 0x00000001

Best Regards,
Olivia

-----Original Message-----
From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-owner@vger.kernel.org] On Behalf Of Bhushan Bharat-R65777

Sent: Tuesday, July 17, 2012 1:10 AM
To: Wood Scott-B07421
Cc: Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org
Subject: RE: [PATCH] openpic: Added BRR1 register



> -----Original Message-----

> From: Wood Scott-B07421

> Sent: Monday, July 16, 2012 10:34 PM

> To: Bhushan Bharat-R65777

> Cc: Alexander Graf; qemu-ppc@nongnu.org; kvm-ppc@vger.kernel.org

> Subject: Re: [PATCH] openpic: Added BRR1 register

> 

> On 07/16/2012 11:21 AM, Bhushan Bharat-R65777 wrote:

> >>> +    case 0x00: /* BRR1 */

> >>> +        retval = 0x00400200;

> >>

> >> Please unmagicify this one :)

> >

> > /* BRR1 ( Block revision register ) */

> >

> > #define IPID 0x00400000 /* IP-block ID */ #define IPMJ 0x00000200 /* 

> > IP major number */ #define IPMN 0x00000200 /* IP minor number */

> 

> IPMN looks wrong.


Opps : copy paste error here :)

Btw, I am not aware of all MPIC IP versions, differences in them and what is the latest/best version this emulated code supports. I drive this value from mpc8544 Reference Manual.

I requested Alex to suggest the most updated version.

Thanks
-Bharat

> 

> -Scott

N     r  y   b X  ǧv ^ )޺{.n +    jir)   w*jg        ݢj/   z ޖ  2 ޙ   & )ߡ a     G   h  j:+v   w ٥

Patch

diff --git a/hw/openpic.c b/hw/openpic.c
index 58ef871..244155b 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -595,6 +595,8 @@  static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
     if (addr & 0xF)
         return;
     switch (addr) {
+    case 0x00: /* BRR1 Readonly */
+        break;
     case 0x40:
     case 0x50:
     case 0x60:
@@ -671,6 +673,7 @@  static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
     case 0x1090: /* PINT */
         retval = 0x00000000;
         break;
+    case 0x00:
     case 0x40:
     case 0x50:
     case 0x60:
@@ -893,6 +896,9 @@  static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
     dst = &opp->dst[idx];
     addr &= 0xFF0;
     switch (addr) {
+    case 0x00: /* BRR1 */
+        retval = 0x00400200;
+        break;
     case 0x80: /* PCTP */
         retval = dst->pctp;
         break;