Patchwork [2/2] build: get dependency file directories from object file names

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Submitter Paolo Bonzini
Date July 11, 2012, 2:40 p.m.
Message ID <1342017621-12650-3-git-send-email-pbonzini@redhat.com>
Download mbox | patch
Permalink /patch/170476/
State New
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Comments

Paolo Bonzini - July 11, 2012, 2:40 p.m.
After commit dcff25f2cd8c11a9368cc2369aeb0319c32d9e26, Dependency file
are taken from the directories that have a Makefile.objs file.  This is
not enough, since files can be included from other directories.
So, pick them from directories that have an object file in them.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 Makefile        |    2 +-
 Makefile.dis    |    3 ---
 Makefile.hw     |    3 ---
 Makefile.target |    3 ---
 Makefile.user   |    3 ---
 rules.mak       |    3 ++-
 6 files changed, 3 insertions(+), 14 deletions(-)
Andreas Färber - July 24, 2012, 11:38 a.m.
Am 11.07.2012 16:40, schrieb Paolo Bonzini:
> After commit dcff25f2cd8c11a9368cc2369aeb0319c32d9e26, Dependency file
> are taken from the directories that have a Makefile.objs file.  This is
> not enough, since files can be included from other directories.
> So, pick them from directories that have an object file in them.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  Makefile        |    2 +-
>  Makefile.dis    |    3 ---
>  Makefile.hw     |    3 ---
>  Makefile.target |    3 ---
>  Makefile.user   |    3 ---
>  rules.mak       |    3 ++-
>  6 files changed, 3 insertions(+), 14 deletions(-)
> 
> diff --git a/Makefile b/Makefile
> index 1b7cd2f..221319e 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -406,5 +406,5 @@ tar:
>  Makefile: $(GENERATED_HEADERS)
>  
>  # Include automatically generated dependency files
> -# All subdir dependencies come automatically from our recursive subdir rules
> --include $(wildcard *.d)
> +# Dependencies in Makefile.objs files come from our recursive subdir rules
> +-include $(wildcard *.d tests/*.d)
> diff --git a/Makefile.dis b/Makefile.dis
> index 09060f0..2cfec6a 100644
> --- a/Makefile.dis
> +++ b/Makefile.dis
> @@ -18,6 +18,3 @@ all: $(libdis-y)
>  
>  clean:
>  	rm -f *.o *.d *.a *~
> -
> -# Include automatically generated dependency files
> --include $(wildcard *.d)
> diff --git a/Makefile.hw b/Makefile.hw
> index 28fe100..59f5b48 100644
> --- a/Makefile.hw
> +++ b/Makefile.hw
> @@ -21,6 +21,3 @@ all: $(hw-obj-y)
>  clean:
>  	rm -f $(addsuffix *.o, $(sort $(dir $(hw-obj-y))))
>  	rm -f $(addsuffix *.d, $(sort $(dir $(hw-obj-y))))
> -
> -# Include automatically generated dependency files
> --include $(patsubst %.o, %.d, $(hw-obj-y))
> diff --git a/Makefile.target b/Makefile.target
> index 74f7a4a..7892a8d 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -214,6 +214,3 @@ endif
>  
>  GENERATED_HEADERS += config-target.h
>  Makefile: $(GENERATED_HEADERS)
> -
> -# Include automatically generated dependency files
> --include $(wildcard *.d fpu/*.d tcg/*.d)
> diff --git a/Makefile.user b/Makefile.user
> index 1783b2a..9302d33 100644
> --- a/Makefile.user
> +++ b/Makefile.user
> @@ -22,6 +22,3 @@ clean:
>  	for d in . trace; do \
>  	rm -f $$d/*.o $$d/*.d $$d/*.a $$d/*~; \
>  	done
> -
> -# Include automatically generated dependency files
> --include $(wildcard *.d)
> diff --git a/rules.mak b/rules.mak
> index 60f3e96..a284946 100644
> --- a/rules.mak
> +++ b/rules.mak
> @@ -94,7 +94,6 @@ define unnest-dir
>  $(foreach var,$(nested-vars),$(call push-var,$(var),$1/))
>  $(eval obj := $(obj)/$1)
>  $(eval include $(SRC_PATH)/$1/Makefile.objs)
> -$(eval -include $(wildcard $1/*.d))
>  $(eval obj := $(patsubst %/$1,%,$(obj)))
>  $(foreach var,$(nested-vars),$(call pop-var,$(var),$1/))
>  endef
> @@ -113,4 +112,6 @@ define unnest-vars
>  $(call unnest-vars-1)
>  $(foreach var,$(nested-vars),$(eval $(var) := $(filter-out %/, $($(var)))))
>  $(shell mkdir -p $(sort $(foreach var,$(nested-vars),$(dir $($(var))))))
> +$(foreach var,$(nested-vars), $(eval \
> +  -include $(addsuffix *.d, $(sort $(dir $($(var)))))))
>  endef
> 

Are you sure? Dependencies are not guaranteed to be in one of the
unnested variables, thought we ran into some issues earlier... In
particular I'm thinking of tcg/*.d and of *.d in .user, .target, those
that are actually recursed into.

Andreas
Paolo Bonzini - July 24, 2012, 11:43 a.m.
Il 24/07/2012 13:38, Andreas Färber ha scritto:
>> > +$(foreach var,$(nested-vars), $(eval \
>> > +  -include $(addsuffix *.d, $(sort $(dir $($(var)))))))
>> >  endef
>> > 
> Are you sure? Dependencies are not guaranteed to be in one of the
> unnested variables, thought we ran into some issues earlier... In
> particular I'm thinking of tcg/*.d and of *.d in .user, .target, those
> that are actually recursed into.

obj-y is a nested variable:

  nested-vars += obj-y

  # This resolves all nested paths, so it must come last
  include $(SRC_PATH)/Makefile.objs

$(dir $(obj-y)) contains tcg/ and from there you get tcg/*.d.

The only makefile that doesn't use the nesting mechanism is tests/Makefile.

Paolo
Andreas Färber - July 24, 2012, 11:53 a.m.
Am 24.07.2012 13:43, schrieb Paolo Bonzini:
> Il 24/07/2012 13:38, Andreas Färber ha scritto:
>>>> +$(foreach var,$(nested-vars), $(eval \
>>>> +  -include $(addsuffix *.d, $(sort $(dir $($(var)))))))
>>>>  endef
>>>>
>> Are you sure? Dependencies are not guaranteed to be in one of the
>> unnested variables, thought we ran into some issues earlier... In
>> particular I'm thinking of tcg/*.d and of *.d in .user, .target, those
>> that are actually recursed into.
> 
> obj-y is a nested variable:
> 
>   nested-vars += obj-y
> 
>   # This resolves all nested paths, so it must come last
>   include $(SRC_PATH)/Makefile.objs
> 
> $(dir $(obj-y)) contains tcg/ and from there you get tcg/*.d.
> 
> The only makefile that doesn't use the nesting mechanism is tests/Makefile.

I think you misunderstood: My worry is

qemu-something: $(obj-y) foo bar baz

obj-y and friends are handled, foo, bar, baz are not. If you checked all
those cases, fine with me. :) Otherwise the new unnesting rule is fine,
but not all "*.d" inclusions could be deleted.

Andreas
Paolo Bonzini - July 24, 2012, 12:02 p.m.
Il 24/07/2012 13:53, Andreas Färber ha scritto:
> Am 24.07.2012 13:43, schrieb Paolo Bonzini:
>> Il 24/07/2012 13:38, Andreas Färber ha scritto:
>>>>> +$(foreach var,$(nested-vars), $(eval \
>>>>> +  -include $(addsuffix *.d, $(sort $(dir $($(var)))))))
>>>>>  endef
>>>>>
>>> Are you sure? Dependencies are not guaranteed to be in one of the
>>> unnested variables, thought we ran into some issues earlier... In
>>> particular I'm thinking of tcg/*.d and of *.d in .user, .target, those
>>> that are actually recursed into.
>>
>> obj-y is a nested variable:
>>
>>   nested-vars += obj-y
>>
>>   # This resolves all nested paths, so it must come last
>>   include $(SRC_PATH)/Makefile.objs
>>
>> $(dir $(obj-y)) contains tcg/ and from there you get tcg/*.d.
>>
>> The only makefile that doesn't use the nesting mechanism is tests/Makefile.
> 
> I think you misunderstood: My worry is
> 
> qemu-something: $(obj-y) foo bar baz
> 
> obj-y and friends are handled, foo, bar, baz are not. If you checked all
> those cases, fine with me. :) Otherwise the new unnesting rule is fine,
> but not all "*.d" inclusions could be deleted.

Ah, yes, I did.  The only cases are in the toplevel Makefile (and the
included tests/Makefile), hence this statement left in that Makefile:

+-include $(wildcard *.d tests/*.d)

Paolo

Patch

diff --git a/Makefile b/Makefile
index 1b7cd2f..221319e 100644
--- a/Makefile
+++ b/Makefile
@@ -406,5 +406,5 @@  tar:
 Makefile: $(GENERATED_HEADERS)
 
 # Include automatically generated dependency files
-# All subdir dependencies come automatically from our recursive subdir rules
--include $(wildcard *.d)
+# Dependencies in Makefile.objs files come from our recursive subdir rules
+-include $(wildcard *.d tests/*.d)
diff --git a/Makefile.dis b/Makefile.dis
index 09060f0..2cfec6a 100644
--- a/Makefile.dis
+++ b/Makefile.dis
@@ -18,6 +18,3 @@  all: $(libdis-y)
 
 clean:
 	rm -f *.o *.d *.a *~
-
-# Include automatically generated dependency files
--include $(wildcard *.d)
diff --git a/Makefile.hw b/Makefile.hw
index 28fe100..59f5b48 100644
--- a/Makefile.hw
+++ b/Makefile.hw
@@ -21,6 +21,3 @@  all: $(hw-obj-y)
 clean:
 	rm -f $(addsuffix *.o, $(sort $(dir $(hw-obj-y))))
 	rm -f $(addsuffix *.d, $(sort $(dir $(hw-obj-y))))
-
-# Include automatically generated dependency files
--include $(patsubst %.o, %.d, $(hw-obj-y))
diff --git a/Makefile.target b/Makefile.target
index 74f7a4a..7892a8d 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -214,6 +214,3 @@  endif
 
 GENERATED_HEADERS += config-target.h
 Makefile: $(GENERATED_HEADERS)
-
-# Include automatically generated dependency files
--include $(wildcard *.d fpu/*.d tcg/*.d)
diff --git a/Makefile.user b/Makefile.user
index 1783b2a..9302d33 100644
--- a/Makefile.user
+++ b/Makefile.user
@@ -22,6 +22,3 @@  clean:
 	for d in . trace; do \
 	rm -f $$d/*.o $$d/*.d $$d/*.a $$d/*~; \
 	done
-
-# Include automatically generated dependency files
--include $(wildcard *.d)
diff --git a/rules.mak b/rules.mak
index 60f3e96..a284946 100644
--- a/rules.mak
+++ b/rules.mak
@@ -94,7 +94,6 @@  define unnest-dir
 $(foreach var,$(nested-vars),$(call push-var,$(var),$1/))
 $(eval obj := $(obj)/$1)
 $(eval include $(SRC_PATH)/$1/Makefile.objs)
-$(eval -include $(wildcard $1/*.d))
 $(eval obj := $(patsubst %/$1,%,$(obj)))
 $(foreach var,$(nested-vars),$(call pop-var,$(var),$1/))
 endef
@@ -113,4 +112,6 @@  define unnest-vars
 $(call unnest-vars-1)
 $(foreach var,$(nested-vars),$(eval $(var) := $(filter-out %/, $($(var)))))
 $(shell mkdir -p $(sort $(foreach var,$(nested-vars),$(dir $($(var))))))
+$(foreach var,$(nested-vars), $(eval \
+  -include $(addsuffix *.d, $(sort $(dir $($(var)))))))
 endef