@@ -223,7 +223,9 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
*/
sPAPRPHBState *phb = opaque;
- qemu_set_irq(phb->lsi_table[irq_num].qirq, level);
+ qemu_set_irq(xics_assign_irq(spapr->icp,
+ phb->lsi_table[irq_num].dt_irq, XICS_LSI),
+ level);
}
static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
@@ -329,16 +331,10 @@ static int spapr_phb_init(SysBusDevice *s)
/* Initialize the LSI table */
for (i = 0; i < PCI_NUM_PINS; i++) {
- qemu_irq qirq;
- uint32_t num;
-
- qirq = spapr_allocate_lsi(0, &num);
- if (!qirq) {
+ if (!spapr_allocate_lsi(0, &phb->lsi_table[i].dt_irq)) {
+ fprintf(stderr, "Failed to allocate LSI IRQ pin %u\n", i);
return -1;
}
-
- phb->lsi_table[i].dt_irq = num;
- phb->lsi_table[i].qirq = qirq;
}
return 0;
@@ -41,7 +41,6 @@ typedef struct sPAPRPHBState {
struct {
uint32_t dt_irq;
- qemu_irq qirq;
} lsi_table[PCI_NUM_PINS];
QLIST_ENTRY(sPAPRPHBState) list;
As it is a very quick operation to resolve qirq from IRQ number, it makes no sense to cache it anywhere but its original source i.e. XICS. Also, the upcoming support for MSIX is going to add much more IRQs per PHB. So we will have to cache them as well for consistency, and for that we will have to create an array of qemu_irq pointers. So it is simplier to keep only IRQ numbers (one per INTx line) and the first MSI IRQ number with vectors number (will be added later). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> --- hw/spapr_pci.c | 14 +++++--------- hw/spapr_pci.h | 1 - 2 files changed, 5 insertions(+), 10 deletions(-)