From patchwork Fri Jul 6 23:04:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen Martin X-Patchwork-Id: 169551 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2588A2C01B4 for ; Sat, 7 Jul 2012 09:05:25 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7DD0F28091; Sat, 7 Jul 2012 01:05:23 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EDnr9y9uVvPE; Sat, 7 Jul 2012 01:05:23 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8AB262808A; Sat, 7 Jul 2012 01:05:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B406E2808A for ; Sat, 7 Jul 2012 01:05:19 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JwYIYzQ2NF0h for ; Sat, 7 Jul 2012 01:05:18 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from hqemgate03.nvidia.com (hqemgate03.nvidia.com [216.228.121.140]) by theia.denx.de (Postfix) with ESMTPS id 0AA6028087 for ; Sat, 7 Jul 2012 01:05:16 +0200 (CEST) Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 06 Jul 2012 16:05:29 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 06 Jul 2012 16:01:35 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 06 Jul 2012 16:01:35 -0700 Received: from nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.264.0; Fri, 6 Jul 2012 16:05:08 -0700 Date: Fri, 6 Jul 2012 16:04:38 -0700 From: Allen Martin To: Stephen Warren Message-ID: <20120706230438.GD29103@nvidia.com> References: <1341598142-28873-1-git-send-email-amartin@nvidia.com> <1341598142-28873-3-git-send-email-amartin@nvidia.com> <4FF737F7.8040008@wwwdotorg.org> <20120706203329.GA29103@nvidia.com> <4FF74E30.3000101@wwwdotorg.org> MIME-Version: 1.0 In-Reply-To: <4FF74E30.3000101@wwwdotorg.org> User-Agent: Mutt/1.5.21 (2010-09-15) Content-Disposition: inline Cc: "u-boot@lists.denx.de" , Tom Warren Subject: Re: [U-Boot] [PATCH 2/7] HACK: rearrange link order for thumb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On Fri, Jul 06, 2012 at 01:44:32PM -0700, Stephen Warren wrote: > On 07/06/2012 02:33 PM, Allen Martin wrote: > > On Fri, Jul 06, 2012 at 12:09:43PM -0700, Stephen Warren wrote: > >> On 07/06/2012 12:08 PM, Allen Martin wrote: > >>> Rearrange the link order of libraries to avoid out of bound > >>> relocations in thumb mode. I have no idea how to fix this for real. > >> > >> Are the relocations branches or something else? It looks like > >> unconditional jump range is +/-4MB for Thumb1 and +/-16MB for Thumb2, so > >> I'm surprised we'd be exceeding that, considering the U-boot binary is > >> on the order of 256KB on Tegra right now. > > > > > > This is the relcation type: > > > > arch/arm/lib/libarm.o: In function `__flush_dcache_all': > > /home/arm/u-boot/arch/arm/lib/cache.c:52: relocation truncated to fit: R_ARM_THM_JUMP11 against symbol `flush_cache' defined in .text section in arch/arm/cpu/armv7/libarmv7.o > > > > The instruction is a "b.n" not a "b", which is what is causing the problem. > > > > I think because of the weak alias the compiler used a short jump to > > the local function, but when it got linked it resolved to a function > > that was too far away for the short jump: > > > > > > void flush_cache(unsigned long start, unsigned long size) > > __attribute__((weak, alias("__flush_cache"))); > > > > 00000002 <__flush_dcache_all>: > > 2: 2000 movs r0, #0 > > 4: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff > > 8: e7fe b.n 0 <__flush_cache> > > Ah, that explanation makes sense. > > > It looks like there's a "-fno-optimize-sibling-calls" option to gcc to > > avoid this problem. Seems a shame to disable all short jumps for this > > one case though. > > It seems like a bug that the b-vs-b.n optimization is applied to a weak > symbol, since the compiler can't possibly know the range of the jump. > > Also, I've seen ld for some architectures rewrite the equivalent of b.n > to plain b when needing to expand the branch target range; IIRC a > process known as "relaxing"? Perhaps gcc is expecting ld to do that, but > ld isn't? I verified the "-fno-optimize-sibling-calls" compiler option works around this. So here's the improved patch: Author: Allen Martin Date: Fri Jul 6 15:58:24 2012 -0700 tegra20: disable local branch optimization This works around a bug when compiling in thumb mode when branching to a weak aliased function. The compiler will optimize the branch to a short branch (b.n instruction) but the linker may resolve the target to a function that is too far away for a short branch. Signed-off-by: Allen Martin diff --git a/arch/arm/cpu/armv7/tegra20/config.mk b/arch/arm/cpu/armv7/tegra20/config.mk index 6432e75..56bb830 100644 --- a/arch/arm/cpu/armv7/tegra20/config.mk +++ b/arch/arm/cpu/armv7/tegra20/config.mk @@ -24,3 +24,8 @@ # MA 02111-1307 USA # CONFIG_ARCH_DEVICE_TREE := tegra20 + +# this works around a bug when compiling thumb where some branches +# are incorrectly optimized to short branches when they shouldn't +# be +PLATFORM_RELFLAGS += -fno-optimize-sibling-calls