From patchwork Thu Jul 5 21:28:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 169277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DC0A52C01BC for ; Fri, 6 Jul 2012 07:29:41 +1000 (EST) Received: from localhost ([::1]:38483 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SmtcJ-00018v-OC for incoming@patchwork.ozlabs.org; Thu, 05 Jul 2012 17:29:39 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48089) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Smtbm-0008Nu-7O for qemu-devel@nongnu.org; Thu, 05 Jul 2012 17:29:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Smtbk-0001vu-B9 for qemu-devel@nongnu.org; Thu, 05 Jul 2012 17:29:05 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:38077) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Smtbk-0001vS-44 for qemu-devel@nongnu.org; Thu, 05 Jul 2012 17:29:04 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Smtbh-0005uo-02; Thu, 05 Jul 2012 22:29:01 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 5 Jul 2012 22:28:59 +0100 Message-Id: <1341523740-22711-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1341523740-22711-1-git-send-email-peter.maydell@linaro.org> References: <1341523740-22711-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Blue Swirl , Stefan Weil , patches@linaro.org Subject: [Qemu-devel] [PATCH 2/3] target-i386: Remove confusing X86_64_DEF macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The X86_64_DEF macro is a confusing way of making some terms in a conditional only appear if TARGET_X86_64 is defined. We only use it in two places, and in both cases this is for making the same test, so abstract that check out into a function where we can use a more conventional #ifdef. Signed-off-by: Peter Maydell --- target-i386/translate.c | 39 ++++++++++++++++++++++++--------------- 1 files changed, 24 insertions(+), 15 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 8d696ea..5899e09 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -38,12 +38,10 @@ #define PREFIX_ADR 0x10 #ifdef TARGET_X86_64 -#define X86_64_DEF(...) __VA_ARGS__ #define CODE64(s) ((s)->code64) #define REX_X(s) ((s)->rex_x) #define REX_B(s) ((s)->rex_b) #else -#define X86_64_DEF(...) #define CODE64(s) 0 #define REX_X(s) 0 #define REX_B(s) 0 @@ -265,11 +263,30 @@ static inline void gen_op_andl_A0_ffff(void) #define REG_LH_OFFSET 4 #endif +/* In instruction encodings for byte register accesses the + * register number usually indicates "low 8 bits of register N"; + * however there are some special cases where N 4..7 indicates + * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return + * true for this special case, false otherwise. + */ +static inline bool byte_reg_is_xH(int reg) +{ + if (reg < 4) { + return false; + } +#ifdef TARGET_X86_64 + if (reg >= 8 || x86_64_hregs) { + return false; + } +#endif + return true; +} + static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) { switch(ot) { case OT_BYTE: - if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { + if (!byte_reg_is_xH(reg)) { tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); } else { tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); @@ -324,19 +341,11 @@ static inline void gen_op_mov_reg_A0(int size, int reg) static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) { - switch(ot) { - case OT_BYTE: - if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { - goto std_case; - } else { - tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); - tcg_gen_ext8u_tl(t0, t0); - } - break; - default: - std_case: + if (ot == OT_BYTE && byte_reg_is_xH(reg)) { + tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); + tcg_gen_ext8u_tl(t0, t0); + } else { tcg_gen_mov_tl(t0, cpu_regs[reg]); - break; } }