| Submitter | Yann Vernier |
|---|---|
| Date | July 5, 2012, 12:11 p.m. |
| Message ID | <201207051448.09389.yann.vernier@orsoc.se> |
| Download | mbox | patch |
| Permalink | /patch/169146/ |
| State | Superseded |
| Delegated to: | Albert ARIBAUD |
| Headers | show |
Comments
On 05.07.2012 14:11, Yann Vernier wrote: > Leave dram_init_banksize to set up the bank info data. > ram_size was previously uninitialized. Also, generalize > lowlevel assembly to support more RAM options. > > Signed-off-by: Yann Vernier <yann.vernier@orsoc.se> > --- > Changes for v2: > - Update to use CONFIG_SYS_SDRAM_ constants > - Update cm41xx also > - Map SDRAM to match configuration > --- > arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 8 +++----- > board/cm4008/cm4008.c | 5 +++-- > board/cm41xx/cm41xx.c | 5 +++-- > include/configs/cm4008.h | 5 ++--- > include/configs/cm41xx.h | 5 ++--- > 5 files changed, 13 insertions(+), 15 deletions(-) > > diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S > index e9f1227..df13de6 100644 > --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S > +++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S > @@ -131,11 +131,9 @@ highflash: > * before relocating, we have to setup RAM timing > */ > ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0) > -#if (PHYS_SDRAM_1_SIZE == 0x02000000) > - ldr r2, =0x7fc0000e /* 32MB */ > -#else > - ldr r2, =0x3fc0000e /* 16MB */ > -#endif > + /* 8 column address bits, 4 banks, 32 bits data width */ > + ldr r2, =((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE-0x10000)<<(22-16) | \ > + (CONFIG_SYS_SDRAM_BASE>>(16-12) | 0x00e)) ugh ... magic. Will it work for every possible setting? How about one setting CONFIG_SYS_SDRAM_BASE != 0x0? I the base address related to register content in any way? Would be great to have a little documentation here why it is shifted that way, unfortunately I can not find a KS8695 spec in the net. Don't get me wrong it is ok to do so. I think it is way better than hard coding the values like before but would be great to understand why it is done that way. Best regards Andreas Bießmann
Patch
diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S index e9f1227..df13de6 100644 --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S @@ -131,11 +131,9 @@ highflash: * before relocating, we have to setup RAM timing */ ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0) -#if (PHYS_SDRAM_1_SIZE == 0x02000000) - ldr r2, =0x7fc0000e /* 32MB */ -#else - ldr r2, =0x3fc0000e /* 16MB */ -#endif + /* 8 column address bits, 4 banks, 32 bits data width */ + ldr r2, =((CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE-0x10000)<<(22-16) | \ + (CONFIG_SYS_SDRAM_BASE>>(16-12) | 0x00e)) str r2, [r1] /* configure sdram bank0 setup */ ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1) mov r2, #0 diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c index ed493a8..6c0da9a 100644 --- a/board/cm4008/cm4008.c +++ b/board/cm4008/cm4008.c @@ -97,8 +97,9 @@ int board_init (void) int dram_init (void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return (0); } diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c index d9dff4e..6aef617 100644 --- a/board/cm41xx/cm41xx.c +++ b/board/cm41xx/cm41xx.c @@ -97,8 +97,9 @@ int board_init (void) int dram_init (void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return (0); } diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h index 408e918..58b0f4b 100644 --- a/include/configs/cm4008.h +++ b/include/configs/cm4008.h @@ -110,9 +110,8 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MB */ #define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */ diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h index d85a600..d29040c 100644 --- a/include/configs/cm41xx.h +++ b/include/configs/cm41xx.h @@ -110,9 +110,8 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_SIZE 0x02000000 /* 32 MB */ #define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
Leave dram_init_banksize to set up the bank info data. ram_size was previously uninitialized. Also, generalize lowlevel assembly to support more RAM options. Signed-off-by: Yann Vernier <yann.vernier@orsoc.se> --- Changes for v2: - Update to use CONFIG_SYS_SDRAM_ constants - Update cm41xx also - Map SDRAM to match configuration --- arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 8 +++----- board/cm4008/cm4008.c | 5 +++-- board/cm41xx/cm41xx.c | 5 +++-- include/configs/cm4008.h | 5 ++--- include/configs/cm41xx.h | 5 ++--- 5 files changed, 13 insertions(+), 15 deletions(-)