From patchwork Tue Jul 3 05:52:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen Martin X-Patchwork-Id: 168698 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CE65D2C0180 for ; Tue, 3 Jul 2012 15:54:38 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 907B5280CD; Tue, 3 Jul 2012 07:54:06 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 31GDVFZc2M6n; Tue, 3 Jul 2012 07:54:06 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2C106280CE; Tue, 3 Jul 2012 07:53:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 474F92808D for ; Tue, 3 Jul 2012 07:53:03 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bxD-EsBljGdH for ; Tue, 3 Jul 2012 07:53:03 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from hqemgate03.nvidia.com (hqemgate03.nvidia.com [216.228.121.140]) by theia.denx.de (Postfix) with ESMTPS id F18152809E for ; Tue, 3 Jul 2012 07:52:57 +0200 (CEST) Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Mon, 02 Jul 2012 22:53:12 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 02 Jul 2012 22:52:56 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 02 Jul 2012 22:52:56 -0700 Received: from badger.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.264.0; Mon, 2 Jul 2012 22:52:55 -0700 From: Allen Martin To: , , , Date: Mon, 2 Jul 2012 22:52:09 -0700 Message-ID: <1341294733-17013-12-git-send-email-amartin@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1341294733-17013-1-git-send-email-amartin@nvidia.com> References: <1341294733-17013-1-git-send-email-amartin@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v6 11/15] tegra20: move SDRAM param save to later in boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Move warmboot_save_sdram_params() to later in the boot sequence. This code relies on devicetree to get the address of the memory controller and with upcoming changes for SPL boot it gets called early in the boot process when devicetree is not initialized yet. Signed-off-by: Allen Martin Acked-by: Stephen Warren --- arch/arm/cpu/tegra20-common/ap20.c | 5 ----- board/nvidia/common/board.c | 3 +++ 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c index 8b6afbc..6ff71e0 100644 --- a/arch/arm/cpu/tegra20-common/ap20.c +++ b/arch/arm/cpu/tegra20-common/ap20.c @@ -345,11 +345,6 @@ void init_pmc_scratch(void) /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ odmdata = get_odmdata(); writel(odmdata, &pmc->pmc_scratch20); - -#ifdef CONFIG_TEGRA20_LP0 - /* save Sdram params to PMC 2, 4, and 24 for WB0 */ - warmboot_save_sdram_params(); -#endif } void tegra20_start(void) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index f349243..03f629d 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -126,6 +126,9 @@ int board_init(void) #endif #ifdef CONFIG_TEGRA20_LP0 + /* save Sdram params to PMC 2, 4, and 24 for WB0 */ + warmboot_save_sdram_params(); + /* prepare the WB code to LP0 location */ warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); #endif