From patchwork Mon Jul 2 17:13:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maksim E. Kozlov" X-Patchwork-Id: 168616 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 858422C009F for ; Tue, 3 Jul 2012 03:13:48 +1000 (EST) Received: from localhost ([::1]:46854 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SlkC2-0001j8-63 for incoming@patchwork.ozlabs.org; Mon, 02 Jul 2012 13:13:46 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37018) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SlkBo-0001gB-Lq for qemu-devel@nongnu.org; Mon, 02 Jul 2012 13:13:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SlkBj-0000Qe-1J for qemu-devel@nongnu.org; Mon, 02 Jul 2012 13:13:32 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:24463) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SlkBi-0000Ps-Rj for qemu-devel@nongnu.org; Mon, 02 Jul 2012 13:13:26 -0400 Received: from eusync4.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6J00HF7MJ5QP80@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Mon, 02 Jul 2012 18:13:53 +0100 (BST) Received: from felix.rnd.samsung.ru ([106.109.9.187]) by eusync4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6J003LYMI3E360@eusync4.samsung.com> for qemu-devel@nongnu.org; Mon, 02 Jul 2012 18:13:23 +0100 (BST) From: Maksim Kozlov To: qemu-devel@nongnu.org Date: Mon, 02 Jul 2012 21:13:15 +0400 Message-id: <1341249195-28088-3-git-send-email-m.kozlov@samsung.com> X-Mailer: git-send-email 1.7.5.4 In-reply-to: <1341249195-28088-1-git-send-email-m.kozlov@samsung.com> References: <1341249195-28088-1-git-send-email-m.kozlov@samsung.com> X-TM-AS-MML: No X-detected-operating-system: by eggs.gnu.org: Solaris 10 (1203?) X-Received-From: 210.118.77.12 Cc: peter.maydell@linaro.org, kyungmin.park@samsung.com, Maksim Kozlov Subject: [Qemu-devel] [PATCH v2 2/2] exynos4210: UART: Added using of CMU-callback functionality X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add using of functionality provided by CMU - get_rate and register_clock_handler. Signed-off-by: Maksim Kozlov --- hw/exynos4210_uart.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 47 insertions(+), 1 deletions(-) diff --git a/hw/exynos4210_uart.c b/hw/exynos4210_uart.c index ccc4780..10581bd 100644 --- a/hw/exynos4210_uart.c +++ b/hw/exynos4210_uart.c @@ -307,6 +307,7 @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s) uint64_t uclk_rate; if (s->reg[I_(UBRDIV)] == 0) { + PRINT_DEBUG("Baud rate division value is 0\n"); return; } @@ -332,7 +333,23 @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s) frame_size += data_bits + stop_bits; - uclk_rate = 24000000; + switch (s->channel) { + case 0: + uclk_rate = exynos4210_cmu_get_rate(EXYNOS4210_SCLK_UART0); + break; + case 1: + uclk_rate = exynos4210_cmu_get_rate(EXYNOS4210_SCLK_UART1); + break; + case 2: + uclk_rate = exynos4210_cmu_get_rate(EXYNOS4210_SCLK_UART2); + break; + case 3: + uclk_rate = exynos4210_cmu_get_rate(EXYNOS4210_SCLK_UART3); + break; + default: + hw_error("%s: Incorrect UART channel: %d\n", + __func__, s->channel); + } speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) + (s->reg[I_(UFRACVAL)] & 0x7) + 16); @@ -348,6 +365,15 @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s) s->channel, speed, parity, data_bits, stop_bits); } +static void uclk_rate_changed(void *opaque) +{ + Exynos4210UartState *s = opaque; + + PRINT_DEBUG("Clock sclk_uart%d was changed\n", s->channel); + + exynos4210_uart_update_parameters(s); +} + static void exynos4210_uart_write(void *opaque, target_phys_addr_t offset, uint64_t val, unsigned size) { @@ -542,6 +568,7 @@ static void exynos4210_uart_reset(DeviceState *dev) container_of(dev, Exynos4210UartState, busdev.qdev); int regs_number = sizeof(exynos4210_uart_regs)/sizeof(Exynos4210UartReg); int i; + Exynos4210Clock clock_id; for (i = 0; i < regs_number; i++) { s->reg[I_(exynos4210_uart_regs[i].offset)] = @@ -551,6 +578,25 @@ static void exynos4210_uart_reset(DeviceState *dev) fifo_reset(&s->rx); fifo_reset(&s->tx); + switch (s->channel) { + case 0: + clock_id = EXYNOS4210_SCLK_UART0; + break; + case 1: + clock_id = EXYNOS4210_SCLK_UART1; + break; + case 2: + clock_id = EXYNOS4210_SCLK_UART2; + break; + case 3: + clock_id = EXYNOS4210_SCLK_UART3; + break; + default: + hw_error("Wrong channel number: %d.\n", s->channel); + } + + exynos4210_register_clock_handler(uclk_rate_changed, clock_id, s); + PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size); }