From patchwork Mon Jul 2 11:36:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 168574 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4A1252C0086 for ; Mon, 2 Jul 2012 21:34:35 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 03688280C2; Mon, 2 Jul 2012 13:34:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iwXKAny6726g; Mon, 2 Jul 2012 13:34:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2BCB3280B6; Mon, 2 Jul 2012 13:34:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BE04E2809E for ; Mon, 2 Jul 2012 13:33:53 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Sp5CViGjKy92 for ; Mon, 2 Jul 2012 13:33:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by theia.denx.de (Postfix) with ESMTP id D61FC280D4 for ; Mon, 2 Jul 2012 13:33:34 +0200 (CEST) Received: from epcpsbgm1.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6J00CQB6RX1XH0@mailout4.samsung.com> for u-boot@lists.denx.de; Mon, 02 Jul 2012 20:33:33 +0900 (KST) X-AuditID: cbfee61a-b7f086d000000e64-da-4ff1870dabd3 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 65.60.03684.D0781FF4; Mon, 02 Jul 2012 20:33:33 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6J00MOX6QL8K70@mmp2.samsung.com> for u-boot@lists.denx.de; Mon, 02 Jul 2012 20:33:33 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Mon, 02 Jul 2012 17:06:42 +0530 Message-id: <1341229005-19008-8-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1341229005-19008-1-git-send-email-rajeshwari.s@samsung.com> References: <1341229005-19008-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMJMWRmVeSWpSXmKPExsVy+t9jQV3e9o/+BjMPc1q83dvJ7sDocfbO DsYAxigum5TUnMyy1CJ9uwSujB+X9jIV/OCv+Hwgv4HxK08XIyeHhICJxPzvR1kgbDGJC/fW s3UxcnEICUxnlPh6YxorhLOKSaJz4hkmkCo2ASOJrSenMYLYIgISEr/6rzKCFDELrGCUmNOz DWyUsECExMcN58EaWARUJXa+/McOYvMKeEgsvLMMap2CxLGpX1lBbE4BT4kZlyeD2UJANbe6 DjBPYORdwMiwilE0tSC5oDgpPddQrzgxt7g0L10vOT93EyPY68+kdjCubLA4xCjAwajEw/ug +aO/EGtiWXFl7iFGCQ5mJRHeDQlAId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rxN1hf8hQTSE0tS s1NTC1KLYLJMHJxSDYyO3j9iDnIYv7Sc4zhV4cSra5fOV+fpP9QIcVhtWnlwj3+sTs7kqj8H vu3t9zfYVeP/Z8/C5OhmNRa5zF0HIw7zXqhekZJ199heu2ATy30+vx+LJgRcTrmQ4Vx9KH6Z FW/aqQru5DOC+u9O9f1wat8x20yi8EHKkp3/XzJNCpDMmvw1Vj/rtpESS3FGoqEWc1FxIgB+ Kheg9gEAAA== X-TM-AS-MML: No Cc: jy0922.shim@samsung.com, patches@linaro.org, jh80.chung@samsung.com, alim.akhtar@samsung.com Subject: [U-Boot] [PATCH 07/10 V5] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde Acked-by: Joonyoung Shim --- Changes in V2: - None Changes in V3: - Incorported review comments from Minkyu Kang. Changes in V4: - None. Changes in V5: - None arch/arm/cpu/armv7/exynos/clock.c | 12 +++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..dbd5f11 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, mpll_fout_sel; switch (pllreg) { case APLL: @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + if (mpll_fout_sel == 0) + fout /= 2; + } + return fout; } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 90271f1..bf41c19 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -596,4 +596,7 @@ struct exynos5_clock { unsigned char res123[0xf5d8]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif