From patchwork Sun Jul 1 02:45:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 168348 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D89882C01BA for ; Sun, 1 Jul 2012 13:23:17 +1000 (EST) Received: from localhost ([::1]:43535 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SlACW-0006hI-ND for incoming@patchwork.ozlabs.org; Sat, 30 Jun 2012 22:47:52 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52527) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SlACI-0006J2-Qz for qemu-devel@nongnu.org; Sat, 30 Jun 2012 22:47:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SlACH-0001gO-42 for qemu-devel@nongnu.org; Sat, 30 Jun 2012 22:47:38 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:41584) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SlACG-0000sO-Rc for qemu-devel@nongnu.org; Sat, 30 Jun 2012 22:47:37 -0400 Received: by mail-pz0-f45.google.com with SMTP id n2so6586109dad.4 for ; Sat, 30 Jun 2012 19:47:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=2LoGdm9uv7vViBX4w+PBPiB5kfiEGosxTmM4KgCaZO4=; b=X+T8Nv+ek/OBNk3qT8hRc175ht9XaQ0tq9T4v+U1yVIRWSHxn2c2D6YGsuCXpwrpuV tta8b3tGmEmA2nb14NbNUSAWCZinrJydEpkFQwBSJ5021Lah/pqGFlSI4xbZRSVf5+uJ k+2UwRp+wJdiMKqNeTI9GSMmRibnShB6M7+y1Ik2r0nzO7/oBfffryUmyeP7O9LhgHYu 8+8Yc3+HmGsNvonFFJEPxsvxabIklwvP2WXIb7V4H5SNbjT8ij3YsABqjU+C14DTmZcO Pnoq3GaWjA5YfpXHVPd0xO1NsjvFmRcPH2IuTOIS4vmARBzph/BpNGO3Heyrsijbzlfp +ADg== Received: by 10.66.84.71 with SMTP id w7mr11631146pay.9.1341110856219; Sat, 30 Jun 2012 19:47:36 -0700 (PDT) Received: from localhost ([118.186.128.232]) by mx.google.com with ESMTPS id og4sm9477291pbb.48.2012.06.30.19.47.33 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 30 Jun 2012 19:47:34 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Sun, 1 Jul 2012 10:45:27 +0800 Message-Id: <1341110730-444-14-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1341110730-444-1-git-send-email-proljc@gmail.com> References: <1341110730-444-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH v8 13/16] target-or32: Add gdb stub support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add OpenRISC gdb stub support. Signed-off-by: Jia Liu --- gdbstub.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index 08cf864..5d37dd9 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1155,6 +1155,68 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n) return sizeof(target_ulong); } +#elif defined(TARGET_OPENRISC) + +#define NUM_CORE_REGS (32 + 3) + +static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + GET_REG32(env->gpr[n]); + } else { + switch (n) { + case 32: /* PPC */ + GET_REG32(env->ppc); + break; + + case 33: /* NPC */ + GET_REG32(env->npc); + break; + + case 34: /* SR */ + GET_REG32(env->sr); + break; + + default: + break; + } + } + return 0; +} + +static int cpu_gdb_write_register(CPUOpenRISCState *env, + uint8_t *mem_buf, int n) +{ + uint32_t tmp; + + if (n > NUM_CORE_REGS) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 32) { + env->gpr[n] = tmp; + } else { + switch (n) { + case 32: /* PPC */ + env->ppc = tmp; + break; + + case 33: /* NPC */ + env->npc = tmp; + break; + + case 34: /* SR */ + env->sr = tmp; + break; + + default: + break; + } + } + return 4; +} #elif defined (TARGET_SH4) /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ @@ -1924,6 +1986,8 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc) } #elif defined (TARGET_MICROBLAZE) s->c_cpu->sregs[SR_PC] = pc; +#elif defined(TARGET_OPENRISC) + s->c_cpu->pc = pc; #elif defined (TARGET_CRIS) s->c_cpu->pc = pc; #elif defined (TARGET_ALPHA)