From patchwork Sun Jul 1 02:45:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 168339 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 07A512C01C7 for ; Sun, 1 Jul 2012 12:46:17 +1000 (EST) Received: from localhost ([::1]:35728 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SlAAw-0002Zt-Mf for incoming@patchwork.ozlabs.org; Sat, 30 Jun 2012 22:46:14 -0400 Received: from eggs.gnu.org ([208.118.235.92]:51949) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SlAAf-0002NL-GF for qemu-devel@nongnu.org; Sat, 30 Jun 2012 22:45:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SlAAd-00010h-GD for qemu-devel@nongnu.org; Sat, 30 Jun 2012 22:45:57 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:55873) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SlAAd-0000wJ-6m for qemu-devel@nongnu.org; Sat, 30 Jun 2012 22:45:55 -0400 Received: by mail-pb0-f45.google.com with SMTP id ro12so6757573pbb.4 for ; Sat, 30 Jun 2012 19:45:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=ETPoK7H7HUtVf7TGy0kEZlkBzbFBxYpPm35TASFjcYs=; b=zXEbn0psnRlw+OWQNsIM+FnwIqBnWdz/5ubIEtclN3a+9V+fzFJA472lZa9a7BMOe/ /hOUKAICqwGQVlnXzjEZAJ8DS69KBApC/cX4gxgR4rOwnb1LFWw4qbEaxCx/wi4lSe/4 ssCDatQ3IppR0VzXmHhXC2PQ0VP3MLrGvwwLY2IRztVQf9qnjwkYLVSu0oCVde46PHNX ozeCMqnQcWNStQAbVPzTJWLygUmc6WNjibrWTpaue/8lOwhxjT/UmGee6hHS+SyAp/Fs 4zQckhqNWUOvqn1FavJa4Nc78tktZ0KZ9ULfBpuuWhA82pCeDTfxIBoU6FXKYQUed82K UCqw== Received: by 10.68.201.7 with SMTP id jw7mr19419862pbc.60.1341110754561; Sat, 30 Jun 2012 19:45:54 -0700 (PDT) Received: from localhost ([118.186.128.232]) by mx.google.com with ESMTPS id wk3sm9484960pbc.21.2012.06.30.19.45.50 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 30 Jun 2012 19:45:53 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Sun, 1 Jul 2012 10:45:16 +0800 Message-Id: <1341110730-444-3-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1341110730-444-1-git-send-email-proljc@gmail.com> References: <1341110730-444-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Subject: [Qemu-devel] [PATCH v8 02/16] target-or32: Add target machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add OpenRISC machine. Signed-off-by: Jia Liu --- target-openrisc/cpu.h | 58 ++++++++++++++++++++++++++++++++++++++++++++- target-openrisc/machine.c | 22 ++++++++++++++++- 2 files changed, 78 insertions(+), 2 deletions(-) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 728e4b3..911f63a 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -67,6 +67,15 @@ typedef struct OpenRISCCPUClass { #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define SET_FP_CAUSE(reg, v) do {\ + (reg) = ((reg) & ~(0x3f << 12)) | \ + ((v & 0x3f) << 12);\ + } while (0) +#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) +#define UPDATE_FP_FLAGS(reg, v) do {\ + (reg) |= ((v & 0x1f) << 2);\ + } while (0) + /* Internal flags, delay slot flag */ #define D_FLAG 1 @@ -137,6 +146,40 @@ enum { IMMUCFGR_HTR = (1 << 11), }; +/* Float point control status register */ +enum { + FPCSR_FPEE = 1, + FPCSR_RM = (3 << 1), + FPCSR_OVF = (1 << 3), + FPCSR_UNF = (1 << 4), + FPCSR_SNF = (1 << 5), + FPCSR_QNF = (1 << 6), + FPCSR_ZF = (1 << 7), + FPCSR_IXF = (1 << 8), + FPCSR_IVF = (1 << 9), + FPCSR_INF = (1 << 10), + FPCSR_DZF = (1 << 11), +}; + +/* Exceptions indices */ +enum { + EXCP_RESET = 0x1, + EXCP_BUSERR = 0x2, + EXCP_DPF = 0x3, + EXCP_IPF = 0x4, + EXCP_TICK = 0x5, + EXCP_ALIGN = 0x6, + EXCP_ILLEGAL = 0x7, + EXCP_INT = 0x8, + EXCP_DTLBMISS = 0x9, + EXCP_ITLBMISS = 0xa, + EXCP_RANGE = 0xb, + EXCP_SYSCALL = 0xc, + EXCP_FPE = 0xd, + EXCP_TRAP = 0xe, + EXCP_NR, +}; + /* Supervisor register */ enum { SR_SM = (1 << 0), @@ -178,12 +221,24 @@ typedef struct CPUOpenRISCState { target_ulong ppc; /* Prev PC */ target_ulong jmp_pc; /* Jump PC */ + target_ulong machi; /* Multiply register MACHI */ + target_ulong maclo; /* Multiply register MACLO */ + + target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */ + target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */ + + target_ulong epcr; /* Exception PC register */ + target_ulong eear; /* Exception EA register */ + uint32_t sr; /* Supervisor register */ uint32_t vr; /* Version register */ uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ uint32_t dmmucfgr; /* DMMU configure register */ uint32_t immucfgr; /* IMMU configure register */ + uint32_t esr; /* Exception supervisor register */ + uint32_t fpcsr; /* Float register */ + float_status fp_status; uint32_t flags; /* cpu_flags, we only use it for exception in solt so far. */ @@ -258,7 +313,8 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, { *pc = env->pc; *cs_base = 0; - *flags = 0; + /* D_FLAG -- branch instruction exception */ + *flags = (env->flags & D_FLAG); } static inline int cpu_mmu_index(CPUOpenRISCState *env) diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c index 11bf275..e5d59a7 100644 --- a/target-openrisc/machine.c +++ b/target-openrisc/machine.c @@ -20,11 +20,31 @@ #include "hw/hw.h" #include "hw/boards.h" +static const VMStateDescription vmstate_cpu = { + .name = "cpu", + .version_id = CPU_SAVE_VERSION, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(gpr, CPUOpenRISCState, 32), + VMSTATE_UINT32(sr, CPUOpenRISCState), + VMSTATE_UINT32(epcr, CPUOpenRISCState), + VMSTATE_UINT32(eear, CPUOpenRISCState), + VMSTATE_UINT32(esr, CPUOpenRISCState), + VMSTATE_UINT32(fpcsr, CPUOpenRISCState), + VMSTATE_UINT32(pc, CPUOpenRISCState), + VMSTATE_UINT32(npc, CPUOpenRISCState), + VMSTATE_UINT32(ppc, CPUOpenRISCState), + VMSTATE_END_OF_LIST() + } +}; + void cpu_save(QEMUFile *f, void *opaque) { + vmstate_save_state(f, &vmstate_cpu, opaque); } int cpu_load(QEMUFile *f, void *opaque, int version_id) { - return 0; + return vmstate_load_state(f, &vmstate_cpu, opaque, version_id); }