Patchwork [U-Boot,07/10,V4] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0

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Submitter Rajeshwari Birje
Date June 29, 2012, 12:59 p.m.
Message ID <1340974750-19969-8-git-send-email-rajeshwari.s@samsung.com>
Download mbox | patch
Permalink /patch/168223/
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Comments

Rajeshwari Birje - June 29, 2012, 12:59 p.m.
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc

Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
Changes in V2:
       - None
Changes in V3:
        -  Incorported review comments from Minkyu Kang.
Changes in V4:
        - None
 arch/arm/cpu/armv7/exynos/clock.c        |   12 +++++++++++-
 arch/arm/include/asm/arch-exynos/clock.h |    3 +++
 2 files changed, 14 insertions(+), 1 deletions(-)
Joon Young Shim - July 2, 2012, 9:52 a.m.
2012/6/29 Rajeshwari Shinde <rajeshwari.s@samsung.com>:
> MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
> Adjust the divisor value to get 800MHz as needed by devices
> like UART etc
>
> Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---
> Changes in V2:
>        - None
> Changes in V3:
>         -  Incorported review comments from Minkyu Kang.
> Changes in V4:
>         - None
>  arch/arm/cpu/armv7/exynos/clock.c        |   12 +++++++++++-
>  arch/arm/include/asm/arch-exynos/clock.h |    3 +++
>  2 files changed, 14 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
> index 330bd75..dbd5f11 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
>         struct exynos5_clock *clk =
>                 (struct exynos5_clock *)samsung_get_base_clock();
>         unsigned long r, m, p, s, k = 0, mask, fout;
> -       unsigned int freq;
> +       unsigned int freq, pll_div2_sel,  mpll_fout_sel;
>
>         switch (pllreg) {
>         case APLL:
> @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
>                 fout = m * (freq / (p * (1 << (s - 1))));
>         }
>
> +       /* According to the user manual, in EVT1 MPLL always gives
> +        * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
> +       if (pllreg == MPLL) {
> +               pll_div2_sel = readl(&clk->pll_div2_sel);
> +               mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
> +                               & MPLL_FOUT_SEL_MASK;
> +               if (mpll_fout_sel == 0)
> +                       fout /= 2;
> +       }
> +
>         return fout;
>  }
>
> diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
> index 90271f1..bf41c19 100644
> --- a/arch/arm/include/asm/arch-exynos/clock.h
> +++ b/arch/arm/include/asm/arch-exynos/clock.h
> @@ -596,4 +596,7 @@ struct exynos5_clock {
>         unsigned char   res123[0xf5d8];
>  };
>  #endif
> +
> +#define MPLL_FOUT_SEL_SHIFT    4
> +#define MPLL_FOUT_SEL_MASK     0x1
>  #endif
> --
> 1.7.4.4
>

Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>

Patch

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..dbd5f11 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@  static unsigned long exynos5_get_pll_clk(int pllreg)
 	struct exynos5_clock *clk =
 		(struct exynos5_clock *)samsung_get_base_clock();
 	unsigned long r, m, p, s, k = 0, mask, fout;
-	unsigned int freq;
+	unsigned int freq, pll_div2_sel,  mpll_fout_sel;
 
 	switch (pllreg) {
 	case APLL:
@@ -155,6 +155,16 @@  static unsigned long exynos5_get_pll_clk(int pllreg)
 		fout = m * (freq / (p * (1 << (s - 1))));
 	}
 
+	/* According to the user manual, in EVT1 MPLL always gives
+	 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+	if (pllreg == MPLL) {
+		pll_div2_sel = readl(&clk->pll_div2_sel);
+		mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+				& MPLL_FOUT_SEL_MASK;
+		if (mpll_fout_sel == 0)
+			fout /= 2;
+	}
+
 	return fout;
 }
 
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index 90271f1..bf41c19 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -596,4 +596,7 @@  struct exynos5_clock {
 	unsigned char	res123[0xf5d8];
 };
 #endif
+
+#define MPLL_FOUT_SEL_SHIFT	4
+#define MPLL_FOUT_SEL_MASK	0x1
 #endif