Patchwork [U-Boot] powerpc/p2041: configure the CPLD lane_mux according to RCW

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Submitter shaohui xie
Date June 29, 2012, 9:37 a.m.
Message ID <1340962645-8014-1-git-send-email-Shaohui.Xie@freescale.com>
Download mbox | patch
Permalink /patch/168028/
State Accepted
Commit 145dbc02501bba43cfee952d5669406c871be6d8
Delegated to: Andy Fleming
Headers show

Comments

shaohui xie - June 29, 2012, 9:37 a.m.
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
is 0xc, CPLD supports SATA by default, we should re-configure the lane
muxing according to RCW, which indicates what SerDes protocol it is running.

Default lane muxing map is as below:
Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
and bit 3 respectively.

Default value of these bits for lane muxing is '1', we should set or clear
these bits accoring to RCW.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
---
 board/freescale/p2041rdb/eth.c |   39 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 39 insertions(+), 0 deletions(-)
Andy Fleming - Aug. 9, 2012, 12:32 a.m.
On Fri, Jun 29, 2012 at 4:37 AM, Shaohui Xie <Shaohui.Xie@freescale.com> wrote:
> Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
> is 0xc, CPLD supports SATA by default, we should re-configure the lane
> muxing according to RCW, which indicates what SerDes protocol it is running.
>
> Default lane muxing map is as below:
> Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
> Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
> Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
> and bit 3 respectively.
>
> Default value of these bits for lane muxing is '1', we should set or clear
> these bits accoring to RCW.
>
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Acked-by: Timur Tabi <timur@freescale.com>

Applied, thanks

Patch

diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 4b0d577..fec9777 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -136,6 +136,11 @@  void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 }
 #endif /* #ifdef CONFIG_FMAN_ENET */
 
+#define CPLD_LANE_A_SEL	0x1
+#define CPLD_LANE_G_SEL	0x2
+#define CPLD_LANE_C_SEL	0x4
+#define CPLD_LANE_D_SEL	0x8
+
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
@@ -143,6 +148,10 @@  int board_eth_init(bd_t *bis)
 	struct tgec_mdio_info tgec_mdio_info;
 	unsigned int i, slot;
 	int lane;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+				FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+	u8 mux = CPLD_READ(serdes_mux);
 
 	printf("Initializing Fman\n");
 
@@ -172,6 +181,36 @@  int board_eth_init(bd_t *bis)
 	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
 	fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
 
+	mux &= ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL);
+	switch (srds_prtcl) {
+	case 0x2:
+	case 0xf:
+		mux &= ~CPLD_LANE_G_SEL;
+		break;
+	case 0x5:
+	case 0x9:
+	case 0xa:
+	case 0x17:
+		mux |= CPLD_LANE_G_SEL;
+		break;
+	case 0x14:
+		mux = (mux & (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL;
+		break;
+	case 0x8:
+	case 0x16:
+	case 0x19:
+	case 0x1a:
+		mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+		break;
+	case 0x1c:
+		mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+		break;
+	default:
+		printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
+		break;
+	}
+	CPLD_WRITE(serdes_mux, mux);
+
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		int idx = i - FM1_DTSEC1;