From patchwork Thu Jun 28 14:35:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 167890 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 60544B6FA4 for ; Fri, 29 Jun 2012 00:36:55 +1000 (EST) Received: from localhost ([::1]:49365 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SkFq1-0002sW-5V for incoming@patchwork.ozlabs.org; Thu, 28 Jun 2012 10:36:53 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SkFpY-0002S1-Ry for qemu-devel@nongnu.org; Thu, 28 Jun 2012 10:36:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SkFpM-000854-P4 for qemu-devel@nongnu.org; Thu, 28 Jun 2012 10:36:24 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:35913) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SkFpM-00083w-IC for qemu-devel@nongnu.org; Thu, 28 Jun 2012 10:36:12 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SkFpG-0008MO-D7; Thu, 28 Jun 2012 15:36:06 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 28 Jun 2012 15:35:57 +0100 Message-Id: <1340894166-32105-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1340894166-32105-1-git-send-email-peter.maydell@linaro.org> References: <1340894166-32105-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: patches@linaro.org Subject: [Qemu-devel] [PATCH 04/13] ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make target_phys_addr_t 64 bits for ARM targets, and set TARGET_PHYS_ADDR_SPACE_BITS to 40. This should have no effect for ARM boards where physical addresses really are 32 bits (except perhaps a slight performance hit on 32 bit hosts for system emulation) but allows us to implement the Large Physical Address Extensions for Cortex-A15, which mean 40 bit physical addresses. Signed-off-by: Peter Maydell --- configure | 2 +- target-arm/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 9f071b7..8b99262 100755 --- a/configure +++ b/configure @@ -3573,7 +3573,7 @@ case "$target_arch2" in bflt="yes" target_nptl="yes" gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" - target_phys_bits=32 + target_phys_bits=64 target_llong_alignment=4 target_libs_softmmu="$fdt_libs" ;; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 33afa18..aadfca0 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -619,7 +619,7 @@ static inline bool cp_access_ok(CPUARMState *env, #define TARGET_PAGE_BITS 10 #endif -#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 40 #define TARGET_VIRT_ADDR_SPACE_BITS 32 static inline CPUARMState *cpu_init(const char *cpu_model)