From patchwork Wed Jun 27 23:50:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 167758 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 32E7D100AA3 for ; Thu, 28 Jun 2012 09:51:04 +1000 (EST) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe001.messaging.microsoft.com [213.199.154.204]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "Microsoft Secure Server Authority" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 520611007EC for ; Thu, 28 Jun 2012 09:50:14 +1000 (EST) Received: from mail14-am1-R.bigfish.com (10.3.201.238) by AM1EHSOBE005.bigfish.com (10.3.204.25) with Microsoft SMTP Server id 14.1.225.23; Wed, 27 Jun 2012 23:48:23 +0000 Received: from mail14-am1 (localhost [127.0.0.1]) by mail14-am1-R.bigfish.com (Postfix) with ESMTP id 4482340373; Wed, 27 Jun 2012 23:48:23 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h944hd25hf0ah) Received: from mail14-am1 (localhost.localdomain [127.0.0.1]) by mail14-am1 (MessageSwitch) id 1340840901762530_6860; Wed, 27 Jun 2012 23:48:21 +0000 (UTC) Received: from AM1EHSMHS013.bigfish.com (unknown [10.3.201.245]) by mail14-am1.bigfish.com (Postfix) with ESMTP id AE30D1E0046; Wed, 27 Jun 2012 23:48:21 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS013.bigfish.com (10.3.207.151) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 27 Jun 2012 23:48:21 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.298.5; Wed, 27 Jun 2012 18:50:04 -0500 Received: from tyr.buserror.net ([10.214.80.172]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q5RNo2nT022284; Wed, 27 Jun 2012 16:50:03 -0700 Date: Wed, 27 Jun 2012 18:50:02 -0500 From: Scott Wood To: Subject: [PATCH 1/3] powerpc/fsl-pci: provide common PCI init Message-ID: <20120627235002.GA9100@tyr.buserror.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20120627234851.GA9071@tyr.buserror.net> User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: freescale.com Cc: linuxppc-dev@lists.ozlabs.org, agraf@suse.de, Jia Hongtao X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15rc1 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" As an alternative incremental starting point to Jia Hongtao's patchset, get the FSL PCI init out of the board files, but do not yet convert to a platform driver. Rather than having each board supply a magic register offset for determining the "primary" bus, we look for which PCI host bridge contains an ISA node within its subtree. If there is no ISA node, normally that would mean there is no primary bus, but until certain bugs are fixed we arbitrarily designate a primary in this case. Conversion to a platform driver and related improvements can happen after this, as the ordering issues are sorted out. Signed-off-by: Scott Wood --- arch/powerpc/sysdev/fsl_pci.c | 66 +++++++++++++++++++++++++++++++++++++++++ arch/powerpc/sysdev/fsl_pci.h | 8 +++++ 2 files changed, 74 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 6073288..f61e407 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -807,3 +807,69 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose) return 0; } + +#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) +static const struct of_device_id pci_ids[] = { + { .compatible = "fsl,mpc8540-pci", }, + { .compatible = "fsl,mpc8548-pcie", }, + { .compatible = "fsl,mpc8610-pci", }, + { .compatible = "fsl,mpc8641-pcie", }, + { .compatible = "fsl,p1022-pcie", }, + { .compatible = "fsl,p1010-pcie", }, + { .compatible = "fsl,p1023-pcie", }, + { .compatible = "fsl,p4080-pcie", }, + { .compatible = "fsl,qoriq-pcie-v2.3", }, + { .compatible = "fsl,qoriq-pcie-v2.2", }, + {}, +}; + +struct device_node *fsl_pci_primary; + +void __devinit fsl_pci_init(void) +{ + struct device_node *node; + struct pci_controller *hose; + dma_addr_t max = 0xffffffff; + + /* If a PCI host bridge has an ISA node under it, it's primary. */ + node = of_find_node_by_type(NULL, "isa"); + while ((fsl_pci_primary = of_get_parent(node))) { + of_node_put(node); + node = fsl_pci_primary; + + if (of_match_node(pci_ids, node)) + break; + } + + node = NULL; + for_each_node_by_type(node, "pci") { + if (of_match_node(pci_ids, node)) { + /* + * If there's no PCI host bridge with ISA, arbitrarily + * designate one as primary. This can go away once + * various bugs with primary-less systems are fixed. + */ + if (!fsl_pci_primary) + fsl_pci_primary = node; + + fsl_add_bridge(node, fsl_pci_primary == node); + hose = pci_find_hose_for_OF_device(node); + max = min(max, hose->dma_window_base_cur + + hose->dma_window_size); + } + } + +#ifdef CONFIG_SWIOTLB + /* + * if we couldn't map all of DRAM via the dma windows + * we need SWIOTLB to handle buffers located outside of + * dma capable memory region + */ + if (memblock_end_of_DRAM() - 1 > max) { + ppc_swiotlb_enable = 1; + set_pci_dma_ops(&swiotlb_dma_ops); + ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; + } +#endif +} +#endif diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index a39ed5c..baa0fd1 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -93,5 +93,13 @@ extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); extern int mpc83xx_add_bridge(struct device_node *dev); u64 fsl_pci_immrbar_base(struct pci_controller *hose); +extern struct device_node *fsl_pci_primary; + +#ifdef CONFIG_FSL_PCI +void fsl_pci_init(void); +#else +static inline void fsl_pci_init(void) {} +#endif + #endif /* __POWERPC_FSL_PCI_H */ #endif /* __KERNEL__ */