From patchwork Wed Jun 27 12:30:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stathis Voukelatos X-Patchwork-Id: 167646 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0C86DB6FA9 for ; Wed, 27 Jun 2012 22:59:16 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A3CC32808D; Wed, 27 Jun 2012 14:59:13 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3XOeo4QzAyL1; Wed, 27 Jun 2012 14:59:13 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CDFC228087; Wed, 27 Jun 2012 14:59:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EAA1028087 for ; Wed, 27 Jun 2012 14:59:07 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eVor85NtWEpJ for ; Wed, 27 Jun 2012 14:59:06 +0200 (CEST) X-Greylist: delayed 1626 seconds by postgrey-1.27 at theia; Wed, 27 Jun 2012 14:59:04 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from linn.co.uk (mail.linn.co.uk [195.59.102.251]) by theia.denx.de (Postfix) with ESMTPS id 6FE6C28084 for ; Wed, 27 Jun 2012 14:59:03 +0200 (CEST) Received: from lhq-exchange.linn.co.uk ([10.2.1.34]) by FortiMail.linn.co.uk with ESMTP id q5RCVExo005469 (version=TLSv1/SSLv3 cipher=RC4-MD5 bits=128 verify=CAFAIL); Wed, 27 Jun 2012 13:31:14 +0100 Received: from lhq-exchange.linn.co.uk ([10.2.1.34]) by lhq-exchange.linn.co.uk ([10.2.1.34]) with mapi; Wed, 27 Jun 2012 13:30:28 +0100 From: Stathis Voukelatos To: "'u-boot@lists.denx.de'" Date: Wed, 27 Jun 2012 13:30:27 +0100 Thread-Topic: [PATCH] i.MX28: bug fixes in PMU configuration code Thread-Index: Ac1UYKRgBjS5H7i1TqSyAVpCGRgszw== Message-ID: <63F28649326B5F45BF5E97E219B5508138E62D2A@lhq-exchange.linn.co.uk> Accept-Language: en-US, en-GB Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US, en-GB MIME-Version: 1.0 Subject: [U-Boot] [PATCH] i.MX28: bug fixes in PMU configuration code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Fixed some typos in the i.MX28 PMU code that sets up the VDDD and VDDIO power rails. In addition the VDDD and VDDIO brownout offset values should be divided by a step size before being programmed to the corresponding registers. Signed-off-by: Stathis Voukelatos Cc: Stefano Babic Cc: Marek Vasut Tested-by: Marek Vasut Acked-by: Marek Vasut --- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 4b09b0c..cc71af8 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -716,7 +716,7 @@ int mx28_get_vddio_power_source_off(void) tmp = readl(&power_regs->hw_power_vddioctrl); if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { return 1; } } @@ -724,7 +724,7 @@ int mx28_get_vddio_power_source_off(void) if (!(readl(&power_regs->hw_power_5vctrl) & POWER_5VCTRL_ENABLE_DCDC)) { if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == - POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) { return 1; } } @@ -772,7 +772,7 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) uint32_t cur_target, diff, bo_int = 0; uint32_t powered_by_linreg = 0; - new_brownout = new_target - new_brownout; + new_brownout = (new_target - new_brownout + 25) / 50; cur_target = readl(&power_regs->hw_power_vddioctrl); cur_target &= POWER_VDDIOCTRL_TRG_MASK; @@ -858,8 +858,8 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) } clrsetbits_le32(&power_regs->hw_power_vddioctrl, - POWER_VDDDCTRL_BO_OFFSET_MASK, - new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); + POWER_VDDIOCTRL_BO_OFFSET_MASK, + new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET); } void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) @@ -869,7 +869,7 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) uint32_t cur_target, diff, bo_int = 0; uint32_t powered_by_linreg = 0; - new_brownout = new_target - new_brownout; + new_brownout = (new_target - new_brownout + 12) / 25; cur_target = readl(&power_regs->hw_power_vdddctrl); cur_target &= POWER_VDDDCTRL_TRG_MASK;