From patchwork Sat Jun 23 23:07:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 166818 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id ED8E4B6F5A for ; Sun, 24 Jun 2012 10:47:50 +1000 (EST) Received: from localhost ([::1]:42933 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiazU-0002p3-Qy for incoming@patchwork.ozlabs.org; Sat, 23 Jun 2012 20:47:48 -0400 Received: from eggs.gnu.org ([208.118.235.92]:38608) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiZRO-0000E6-Jp for qemu-devel@nongnu.org; Sat, 23 Jun 2012 19:08:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SiZRH-0002Vs-A0 for qemu-devel@nongnu.org; Sat, 23 Jun 2012 19:08:30 -0400 Received: from cantor2.suse.de ([195.135.220.15]:34944 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiZRG-0002VB-R6; Sat, 23 Jun 2012 19:08:23 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 8CFFEA4386; Sun, 24 Jun 2012 01:08:21 +0200 (CEST) From: Alexander Graf To: qemu-devel qemu-devel Date: Sun, 24 Jun 2012 01:07:23 +0200 Message-Id: <1340492856-21126-60-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1340492856-21126-1-git-send-email-agraf@suse.de> References: <1340492856-21126-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Blue Swirl , qemu-ppc Mailing List , Aurelien Jarno Subject: [Qemu-devel] [PATCH 59/72] PPC: e500: Extend address/size of / to 64bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We want to be able to support >= 4GB of RAM. To do so, we need to be able to tell the guest OS how much RAM it has. However, that information today is capped to 32bit. So let's extend the offset and size fields to 64bit, so we can fit in big addresses and even one day - if we wish to do so - map devices above 32bit. Signed-off-by: Alexander Graf --- hw/ppce500_mpc8544ds.c | 28 ++++++++++++++++++---------- 1 files changed, 18 insertions(+), 10 deletions(-) diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index c6a09bb..bf48bc7 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -90,7 +90,7 @@ static int mpc8544_load_device_tree(CPUPPCState *env, const char *kernel_cmdline) { int ret = -1; - uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)}; + uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) }; int fdt_size; void *fdt; uint8_t hypercall[16]; @@ -108,9 +108,16 @@ static int mpc8544_load_device_tree(CPUPPCState *env, char gutil[128]; char pci[128]; uint32_t pci_map[9 * 8]; - uint32_t pci_ranges[12] = { 0x2000000, 0x0, 0xc0000000, 0xc0000000, 0x0, - 0x20000000, 0x1000000, 0x0, 0x0, 0xe1000000, - 0x0, 0x10000 }; + uint32_t pci_ranges[14] = + { + 0x2000000, 0x0, 0xc0000000, + 0x0, 0xc0000000, + 0x0, 0x20000000, + + 0x1000000, 0x0, 0x0, + 0x0, 0xe1000000, + 0x0, 0x10000, + }; QemuOpts *machine_opts; const char *dumpdtb = NULL; const char *dtb_file = NULL; @@ -144,8 +151,8 @@ static int mpc8544_load_device_tree(CPUPPCState *env, qemu_devtree_setprop_string(fdt, "/", "model", model); qemu_devtree_setprop(fdt, "/", "compatible", compatible, sizeof(compatible)); - qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 1); - qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 1); + qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); + qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); qemu_devtree_add_subnode(fdt, "/memory"); qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); @@ -239,7 +246,8 @@ static int mpc8544_load_device_tree(CPUPPCState *env, sizeof(compatible_sb)); qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); - qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, MPC8544_CCSRBAR_BASE, + qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, + MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, MPC8544_CCSRBAR_SIZE); /* XXX should contain a reasonable value */ qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); @@ -313,12 +321,12 @@ static int mpc8544_load_device_tree(CPUPPCState *env, qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic); qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2, 0, 0); qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); - for (i = 0; i < 12; i++) { + for (i = 0; i < 14; i++) { pci_ranges[i] = cpu_to_be32(pci_ranges[i]); } qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); - qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE, - 0x1000); + qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, + MPC8544_PCI_REGS_BASE, 0, 0x1000); qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);