From patchwork Sat Jun 23 23:07:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 166815 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 54851B6F9F for ; Sun, 24 Jun 2012 10:41:18 +1000 (EST) Received: from localhost ([::1]:38992 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiatA-0000c2-6D for incoming@patchwork.ozlabs.org; Sat, 23 Jun 2012 20:41:16 -0400 Received: from eggs.gnu.org ([208.118.235.92]:38882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiZRW-0000PW-KX for qemu-devel@nongnu.org; Sat, 23 Jun 2012 19:08:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SiZRO-0002an-E2 for qemu-devel@nongnu.org; Sat, 23 Jun 2012 19:08:38 -0400 Received: from cantor2.suse.de ([195.135.220.15]:34977 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SiZRO-0002a2-6D; Sat, 23 Jun 2012 19:08:30 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id E2FFF9B4B4; Sun, 24 Jun 2012 01:08:28 +0200 (CEST) From: Alexander Graf To: qemu-devel qemu-devel Date: Sun, 24 Jun 2012 01:07:35 +0200 Message-Id: <1340492856-21126-72-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1340492856-21126-1-git-send-email-agraf@suse.de> References: <1340492856-21126-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Blue Swirl , qemu-ppc Mailing List , Aurelien Jarno Subject: [Qemu-devel] [PATCH 71/72] PPC: BookE: Support 32 and 64 bit wide MAS2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The MAS registers on BookE are all 32 bit wide, except for MAS2, which can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR setting code, so that the guest can never write invalid values in them. Signed-off-by: Alexander Graf --- target-ppc/translate_init.c | 19 ++++++++++++++++++- 1 files changed, 18 insertions(+), 1 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 8ff47ae..e6580ff 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -86,6 +86,19 @@ static void spr_write_generic (void *opaque, int sprn, int gprn) } #if !defined(CONFIG_USER_ONLY) +static void spr_write_generic32(void *opaque, int sprn, int gprn) +{ +#ifdef TARGET_PPC64 + TCGv t0 = tcg_temp_new(); + tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); + gen_store_spr(sprn, t0); + tcg_temp_free(t0); + spr_store_dump_spr(sprn); +#else + spr_write_generic(opaque, sprn, gprn); +#endif +} + static void spr_write_clear (void *opaque, int sprn, int gprn) { TCGv t0 = tcg_temp_new(); @@ -1597,10 +1610,14 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, /* TLB assist registers */ /* XXX : not implemented */ for (i = 0; i < 8; i++) { + void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32; + if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { + uea_write = &spr_write_generic; + } if (mas_mask & (1 << i)) { spr_register(env, mas_sprn[i], mas_names[i], SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, uea_write, 0x00000000); } }