@@ -133,7 +133,6 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
-#if !defined(CONFIG_TEGRA20)
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -149,7 +148,6 @@ reset:
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
-#endif /* !Tegra20 */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
@@ -20,16 +20,11 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
-#include <asm/arch/clock.h>
#include <asm/arch/fuse.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pmc.h>
-#include <asm/arch/pinmux.h>
#include <asm/arch/scu.h>
#include <asm/arch/warmboot.h>
#include <common.h>
@@ -68,235 +63,7 @@ int tegra_get_chip_type(void)
return TEGRA_SOC_UNKNOWN;
}
-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-static int ap20_cpu_is_cortexa9(void)
-{
- u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
- return id == (PG_UP_TAG_0_PID_CPU & 0xff);
-}
-
-void init_pllx(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll_simple *pll =
- &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
- u32 reg;
-
- /* If PLLX is already enabled, just return */
- if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
- return;
-
- /* Set PLLX_MISC */
- writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
-
- /* Use 12MHz clock here */
- reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
- reg |= 1000 << PLL_DIVN_SHIFT;
- writel(reg, &pll->pll_base);
-
- reg |= PLL_ENABLE_MASK;
- writel(reg, &pll->pll_base);
-
- reg &= ~PLL_BYPASS_MASK;
- writel(reg, &pll->pll_base);
-}
-
-static void enable_cpu_clock(int enable)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 clk;
-
- /*
- * NOTE:
- * Regardless of whether the request is to enable or disable the CPU
- * clock, every processor in the CPU complex except the master (CPU 0)
- * will have it's clock stopped because the AVP only talks to the
- * master. The AVP does not know (nor does it need to know) that there
- * are multiple processors in the CPU complex.
- */
-
- if (enable) {
- /* Initialize PLLX */
- init_pllx();
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
- }
-
- /*
- * Read the register containing the individual CPU clock enables and
- * always stop the clock to CPU 1.
- */
- clk = readl(&clkrst->crc_clk_cpu_cmplx);
- clk |= 1 << CPU1_CLK_STP_SHIFT;
-
- /* Stop/Unstop the CPU clock */
- clk &= ~CPU0_CLK_STP_MASK;
- clk |= !enable << CPU0_CLK_STP_SHIFT;
- writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
- clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
-
- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
- u32 reg;
-
- /* Remove the clamps on the CPU I/O signals */
- reg = readl(&pmc->pmc_remove_clamping);
- reg |= CPU_CLMP;
- writel(reg, &pmc->pmc_remove_clamping);
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-}
-
-static void powerup_cpu(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
- u32 reg;
- int timeout = IO_STABILIZATION_DELAY;
-
- if (!is_cpu_powered()) {
- /* Toggle the CPU power state (OFF -> ON) */
- reg = readl(&pmc->pmc_pwrgate_toggle);
- reg &= PARTID_CP;
- reg |= START_CP;
- writel(reg, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_cpu_powered()) {
- if (timeout-- == 0)
- printf("CPU failed to power up!\n");
- else
- udelay(10);
- }
-
- /*
- * Remove the I/O clamps from CPU power partition.
- * Recommended only on a Warm boot, if the CPU partition gets
- * power gated. Shouldn't cause any harm when called after a
- * cold boot according to HW, probably just redundant.
- */
- remove_cpu_io_clamps();
- }
-}
-
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
- u32 reg;
-
- reg = readl(&pmc->pmc_cntrl);
- reg |= CPUPWRREQ_OE;
- writel(reg, &pmc->pmc_cntrl);
-
- /*
- * The TI PMU65861C needs a 3.75ms delay between enabling
- * the power rail and enabling the CPU clock. This delay
- * between SM1EN and SM1 is for switching time + the ramp
- * up of the voltage to the CPU (VDD_CPU from PMU).
- */
- udelay(3750);
-}
-
-static void reset_A9_cpu(int reset)
-{
- /*
- * NOTE: Regardless of whether the request is to hold the CPU in reset
- * or take it out of reset, every processor in the CPU complex
- * except the master (CPU 0) will be held in reset because the
- * AVP only talks to the master. The AVP does not know that there
- * are multiple processors in the CPU complex.
- */
-
- /* Hold CPU 1 in reset, and CPU 0 if asked */
- reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
- reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
- reset);
-
- /* Enable/Disable master CPU reset */
- reset_set_enable(PERIPH_ID_CPU, reset);
-}
-
-static void clock_enable_coresight(int enable)
-{
- u32 rst, src;
-
- clock_set_enable(PERIPH_ID_CORESIGHT, enable);
- reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
-
- if (enable) {
- /*
- * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
- * 1.5, giving an effective frequency of 144MHz.
- * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
- * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
- */
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
- clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
-
- /* Unlock the CPU CoreSight interfaces */
- rst = 0xC5ACCE55;
- writel(rst, CSITE_CPU_DBG0_LAR);
- writel(rst, CSITE_CPU_DBG1_LAR);
- }
-}
-
-void start_cpu(u32 reset_vector)
-{
- /* Enable VDD_CPU */
- enable_cpu_power_rail();
-
- /* Hold the CPUs in reset */
- reset_A9_cpu(1);
-
- /* Disable the CPU clock */
- enable_cpu_clock(0);
-
- /* Enable CoreSight */
- clock_enable_coresight(1);
-
- /*
- * Set the entry point for CPU execution from reset,
- * if it's a non-zero value.
- */
- if (reset_vector)
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
- /* Enable the CPU clock */
- enable_cpu_clock(1);
-
- /* If the CPU doesn't already have power, power it up */
- powerup_cpu();
-
- /* Take the CPU out of reset */
- reset_A9_cpu(0);
-}
-
-
-void halt_avp(void)
-{
- for (;;) {
- writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
- | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
- FLOW_CTLR_HALT_COP_EVENTS);
- }
-}
-
-void enable_scu(void)
+static void enable_scu(void)
{
struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
u32 reg;
@@ -332,7 +99,7 @@ static u32 get_odmdata(void)
return odmdata;
}
-void init_pmc_scratch(void)
+static void init_pmc_scratch(void)
{
struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
u32 odmdata;
@@ -347,27 +114,8 @@ void init_pmc_scratch(void)
writel(odmdata, &pmc->pmc_scratch20);
}
-void tegra20_start(void)
+void lowlevel_init(void)
{
- struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-
- /* If we are the AVP, start up the first Cortex-A9 */
- if (!ap20_cpu_is_cortexa9()) {
- /* enable JTAG */
- writel(0xC0, &pmt->pmt_cfg_ctl);
-
- /*
- * If we are ARM7 - give it a different stack. We are about to
- * start up the A9 which will want to use this one.
- */
- asm volatile("mov sp, %0\n"
- : : "r"(AVP_EARLY_BOOT_STACK_LIMIT));
-
- start_cpu((u32)_start);
- halt_avp();
- /* not reached */
- }
-
/* Init PMC scratch memory */
init_pmc_scratch();
@@ -23,12 +23,12 @@
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pmc.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/tegra20.h>
+#include <asm/arch/warmboot.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -80,27 +80,6 @@ int checkboard(void)
}
#endif /* CONFIG_DISPLAY_BOARDINFO */
-#ifdef CONFIG_ARCH_CPU_INIT
-/*
- * Note this function is executed by the ARM7TDMI AVP. It does not return
- * in this case. It is also called once the A9 starts up, but does nothing in
- * that case.
- */
-int arch_cpu_init(void)
-{
- /* Fire up the Cortex A9 */
- tegra20_start();
-
- /* We didn't do this init in start.S, so do it now */
- cpu_init_cp15();
-
- /* Initialize essential common plls */
- clock_early_init();
-
- return 0;
-}
-#endif
-
static int uart_configs[] = {
#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
@@ -233,10 +233,10 @@ s5pc210_universal arm armv7 universal_c210 samsung
smdk5250 arm armv7 smdk5250 samsung exynos
smdkv310 arm armv7 smdkv310 samsung exynos
trats arm armv7 trats samsung exynos
-harmony arm armv7 harmony nvidia tegra20
-seaboard arm armv7 seaboard nvidia tegra20
-ventana arm armv7 ventana nvidia tegra20
-whistler arm armv7 whistler nvidia tegra20
+harmony arm armv7:arm720t harmony nvidia tegra20
+seaboard arm armv7:arm720t seaboard nvidia tegra20
+ventana arm armv7:arm720t ventana nvidia tegra20
+whistler arm armv7:arm720t whistler nvidia tegra20
u8500_href arm armv7 u8500 st-ericsson u8500
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
@@ -262,11 +262,11 @@ xaeniax arm pxa
zipitz2 arm pxa
colibri_pxa270 arm pxa - toradex
jornada arm sa1100
-plutux arm armv7 plutux avionic-design tegra20
-medcom arm armv7 medcom avionic-design tegra20
-tec arm armv7 tec avionic-design tegra20
-paz00 arm armv7 paz00 compal tegra20
-trimslice arm armv7 trimslice compulab tegra20
+plutux arm armv7:arm720t plutux avionic-design tegra20
+medcom arm armv7:arm720t medcom avionic-design tegra20
+tec arm armv7:arm720t tec avionic-design tegra20
+paz00 arm armv7:arm720t paz00 compal tegra20
+trimslice arm armv7:arm720t trimslice compulab tegra20
atngw100 avr32 at32ap - atmel at32ap700x
atstk1002 avr32 at32ap atstk1000 atmel at32ap700x
atstk1003 avr32 at32ap atstk1000 atmel at32ap700x
@@ -144,4 +144,69 @@
TEGRA20_DEVICE_SETTINGS \
BOOTCMDS_COMMON
+/* overrides for SPL build here */
+#ifdef CONFIG_SPL_BUILD
+
+/* remove devicetree support */
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_CONTROL
+#endif
+
+/* remove SERIAL_MULTI */
+#ifdef CONFIG_SERIAL_MULTI
+#undef CONFIG_SERIAL_MULTI
+#endif
+
+/* remove I2C support */
+#ifdef CONFIG_TEGRA_I2C
+#undef CONFIG_TEGRA_I2C
+#endif
+#ifdef CONFIG_CMD_I2C
+#undef CONFIG_CMD_I2C
+#endif
+
+/* remove MMC support */
+#ifdef CONFIG_MMC
+#undef CONFIG_MMC
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#undef CONFIG_GENERIC_MMC
+#endif
+#ifdef CONFIG_TEGRA20_MMC
+#undef CONFIG_TEGRA20_MMC
+#endif
+#ifdef CONFIG_CMD_MMC
+#undef CONFIG_CMD_MMC
+#endif
+
+/* remove partitions/filesystems */
+#ifdef CONFIG_DOS_PARTITION
+#undef CONFIG_DOS_PARTITION
+#endif
+#ifdef CONFIG_EFI_PARTITION
+#undef CONFIG_EFI_PARTITION
+#endif
+#ifdef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_EXT2
+#endif
+#ifdef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FAT
+#endif
+
+/* remove USB */
+#ifdef CONFIG_USB_EHCI
+#undef CONFIG_USB_EHCI
+#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+#undef CONFIG_USB_EHCI_TEGRA
+#endif
+#ifdef CONFIG_USB_STORAGE
+#undef CONFIG_USB_STORAGE
+#endif
+#ifdef CONFIG_CMD_USB
+#undef CONFIG_CMD_USB
+#endif
+
+#endif /* CONFIG_SPL_BUILD */
+
#endif /* __TEGRA20_COMMON_POST_H */
@@ -43,8 +43,6 @@
#define CONFIG_SYS_CACHELINE_SIZE 32
-#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */
-
#include <asm/arch/tegra20.h> /* get chip and board defs */
/*
@@ -53,8 +51,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
@@ -183,7 +179,7 @@
#define PHYS_SDRAM_1 TEGRA20_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_TEXT_BASE 0x00108000
+#define CONFIG_SYS_TEXT_BASE 0x0010c000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
@@ -195,4 +191,20 @@
#define CONFIG_TEGRA_GPIO
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_ENTERRCM
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE 0x00108000
+#define CONFIG_SPL_MAX_SIZE 0x00004000
+#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
+#define CONFIG_SPL_STACK 0x000ffffc
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
+
#endif /* __TEGRA20_COMMON_H */
Add SPL options to tegra20 config files and enable SPL build for tegra20 boards in boards.cfg. Also remove redundant code from u-boot that is not contained in SPL. Signed-off-by: Allen Martin <amartin@nvidia.com> --- arch/arm/cpu/armv7/start.S | 2 - arch/arm/cpu/tegra20-common/ap20.c | 258 +-------------------------------- arch/arm/cpu/tegra20-common/board.c | 23 +-- boards.cfg | 18 +-- include/configs/tegra20-common-post.h | 65 +++++++++ include/configs/tegra20-common.h | 22 ++- 6 files changed, 95 insertions(+), 293 deletions(-)