Comments
Patch
@@ -345,11 +345,6 @@ void init_pmc_scratch(void)
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
odmdata = get_odmdata();
writel(odmdata, &pmc->pmc_scratch20);
-
-#ifdef CONFIG_TEGRA20_LP0
- /* save Sdram params to PMC 2, 4, and 24 for WB0 */
- warmboot_save_sdram_params();
-#endif
}
void tegra20_start(void)
@@ -126,6 +126,9 @@ int board_init(void)
#endif
#ifdef CONFIG_TEGRA20_LP0
+ /* save Sdram params to PMC 2, 4, and 24 for WB0 */
+ warmboot_save_sdram_params();
+
/* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif
Move warmboot_save_sdram_params() to later in the boot sequence. This code relies on devicetree to get the address of the memory controller and with upcoming changes for SPL boot it gets called early in the boot process when devicetree is not initialized yet. Signed-off-by: Allen Martin <amartin@nvidia.com> --- arch/arm/cpu/tegra20-common/ap20.c | 5 ----- board/nvidia/common/board.c | 3 +++ 2 files changed, 3 insertions(+), 5 deletions(-)