From patchwork Thu Jun 21 13:33:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 166341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CE9F6B6FA0 for ; Fri, 22 Jun 2012 00:52:59 +1000 (EST) Received: from localhost ([::1]:51812 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShhXg-0007p2-OL for incoming@patchwork.ozlabs.org; Thu, 21 Jun 2012 09:35:24 -0400 Received: from eggs.gnu.org ([208.118.235.92]:51089) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShhWb-0005Yr-33 for qemu-devel@nongnu.org; Thu, 21 Jun 2012 09:34:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ShhWU-0002Dx-18 for qemu-devel@nongnu.org; Thu, 21 Jun 2012 09:34:16 -0400 Received: from cantor2.suse.de ([195.135.220.15]:54217 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShhWT-0002D3-OG; Thu, 21 Jun 2012 09:34:09 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 5F078A3B99; Thu, 21 Jun 2012 15:34:08 +0200 (CEST) From: Alexander Graf To: qemu-devel qemu-devel Date: Thu, 21 Jun 2012 15:33:54 +0200 Message-Id: <1340285640-28669-6-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1340285640-28669-1-git-send-email-agraf@suse.de> References: <1340285640-28669-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Caraman Mihai Claudiu-B02008 , qemu-ppc Mailing List Subject: [Qemu-devel] [PATCH v2 05/11] PPC: Add support for MSR_CM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The BookE variant of MSR_SF is MSR_CM. Implement everything it takes in TCG to support running 64bit code with MSR_CM set. Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 9 +++++++++ target-ppc/excp_helper.c | 9 +++++---- target-ppc/mem_helper.c | 2 +- target-ppc/translate.c | 2 +- 4 files changed, 16 insertions(+), 6 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 12200ab..7a77fff 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2212,6 +2212,15 @@ static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn) #endif +static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) +{ + if (env->mmu_model == POWERPC_MMU_BOOKE206) { + return msr & (1ULL << MSR_CM); + } + + return msr & (1ULL << MSR_SF); +} + extern void (*cpu_ppc_hypercall)(CPUPPCState *); static inline bool cpu_has_work(CPUPPCState *env) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index c7762b9..1a593f6 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -608,10 +608,11 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) vector |= env->excp_prefix; #if defined(TARGET_PPC64) if (excp_model == POWERPC_EXCP_BOOKE) { - if (!msr_icm) { - vector = (uint32_t)vector; - } else { + if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { + /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ new_msr |= (target_ulong)1 << MSR_CM; + } else { + vector = (uint32_t)vector; } } else { if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { @@ -803,7 +804,7 @@ static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr, target_ulong msrm, int keep_msrh) { #if defined(TARGET_PPC64) - if (msr & (1ULL << MSR_SF)) { + if (msr_is_64bit(env, msr)) { nip = (uint64_t)nip; msr &= (uint64_t)msrm; } else { diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c index ebcd7b2..5b5f1bd 100644 --- a/target-ppc/mem_helper.c +++ b/target-ppc/mem_helper.c @@ -35,7 +35,7 @@ static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr, target_long arg) { #if defined(TARGET_PPC64) - if (!msr_sf) { + if (!msr_is_64bit(env, env->msr)) { return (uint32_t)(addr + arg); } else #endif diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9103fd5..73ee74b 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9626,7 +9626,7 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env, ctx.access_type = -1; ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; #if defined(TARGET_PPC64) - ctx.sf_mode = msr_sf; + ctx.sf_mode = msr_is_64bit(env, env->msr); ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); #endif ctx.fpu_enabled = msr_fp;