Patchwork [7/8] PPC: Turn hardcoded reset mask into env variable

login
register
mail settings
Submitter Alexander Graf
Date June 20, 2012, 8:11 p.m.
Message ID <1340223111-13449-8-git-send-email-agraf@suse.de>
Download mbox | patch
Permalink /patch/166147/
State New
Headers show

Comments

Alexander Graf - June 20, 2012, 8:11 p.m.
Some machines have MSR bits they reset with as enabled. Don't hardcode the
logic, but let the individual core implementations save their own reset
mask into an env variable.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-ppc/cpu.h            |    1 +
 target-ppc/translate_init.c |   14 ++++++++------
 2 files changed, 9 insertions(+), 6 deletions(-)
Blue Swirl - June 21, 2012, 6:09 p.m.
On Wed, Jun 20, 2012 at 8:11 PM, Alexander Graf <agraf@suse.de> wrote:
> Some machines have MSR bits they reset with as enabled. Don't hardcode the
> logic, but let the individual core implementations save their own reset
> mask into an env variable.
>
> Signed-off-by: Alexander Graf <agraf@suse.de>
> ---
>  target-ppc/cpu.h            |    1 +
>  target-ppc/translate_init.c |   14 ++++++++------
>  2 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 652a35a..acf5816 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1043,6 +1043,7 @@ struct CPUPPCState {
>  #if defined(TARGET_PPC64)
>     struct ppc_segment_page_sizes sps;
>  #endif
> +    uint64_t reset_msr;
>
>  #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
>     target_phys_addr_t vpa;
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 57027a2..efa05fc 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -6273,6 +6273,7 @@ static void init_proc_970 (CPUPPCState *env)
>     env->slb_nr = 32;
>  #endif
>     init_excp_970(env);
> +    env->reset_msr = (1ULL < MSR_SF);

The parenthesis are not necessary.

>     env->dcache_line_size = 128;
>     env->icache_line_size = 128;
>     /* Allocate hardware IRQ controller */
> @@ -6375,6 +6376,7 @@ static void init_proc_970FX (CPUPPCState *env)
>     env->slb_nr = 64;
>  #endif
>     init_excp_970(env);
> +    env->reset_msr = (1ULL < MSR_SF);
>     env->dcache_line_size = 128;
>     env->icache_line_size = 128;
>     /* Allocate hardware IRQ controller */
> @@ -6465,6 +6467,7 @@ static void init_proc_970GX (CPUPPCState *env)
>     env->slb_nr = 32;
>  #endif
>     init_excp_970(env);
> +    env->reset_msr = (1ULL < MSR_SF);
>     env->dcache_line_size = 128;
>     env->icache_line_size = 128;
>     /* Allocate hardware IRQ controller */
> @@ -6555,6 +6558,7 @@ static void init_proc_970MP (CPUPPCState *env)
>     env->slb_nr = 32;
>  #endif
>     init_excp_970(env);
> +    env->reset_msr = (1ULL < MSR_SF);
>     env->dcache_line_size = 128;
>     env->icache_line_size = 128;
>     /* Allocate hardware IRQ controller */
> @@ -6640,6 +6644,7 @@ static void init_proc_POWER7 (CPUPPCState *env)
>     env->slb_nr = 32;
>  #endif
>     init_excp_POWER7(env);
> +    env->reset_msr = (1ULL < MSR_SF);
>     env->dcache_line_size = 128;
>     env->icache_line_size = 128;
>     /* Allocate hardware IRQ controller */
> @@ -6686,6 +6691,7 @@ static void init_proc_620 (CPUPPCState *env)
>     /* Memory management */
>     gen_low_BATs(env);
>     init_excp_620(env);
> +    env->reset_msr = (1ULL < MSR_SF);
>     env->dcache_line_size = 64;
>     env->icache_line_size = 64;
>     /* Allocate hardware IRQ controller */
> @@ -9306,6 +9312,7 @@ static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
>     env->nb_BATs = 0;
>     env->nb_tlb = 0;
>     env->nb_ways = 0;
> +    env->reset_msr = 0;
>     env->tlb_type = TLB_NONE;
>  #endif
>     /* Register SPR common to all PowerPC implementations */
> @@ -10246,7 +10253,7 @@ static void ppc_cpu_reset(CPUState *s)
>
>     pcc->parent_reset(s);
>
> -    msr = (target_ulong)0;
> +    msr = (target_ulong)env->reset_msr;
>     if (0) {
>         /* XXX: find a suitable condition to enable the hypervisor mode */
>         msr |= (target_ulong)MSR_HVB;
> @@ -10272,11 +10279,6 @@ static void ppc_cpu_reset(CPUState *s)
>     }
>  #endif
>     env->msr = msr & env->msr_mask;
> -#if defined(TARGET_PPC64)
> -    if (env->mmu_model & POWERPC_MMU_64) {
> -        env->msr |= (1ULL << MSR_SF);
> -    }
> -#endif
>     hreg_compute_hflags(env);
>     env->reserve_addr = (target_ulong)-1ULL;
>     /* Be sure no exception or interrupt is pending */
> --
> 1.6.0.2
>
>
Peter Maydell - June 21, 2012, 6:16 p.m.
On 20 June 2012 21:11, Alexander Graf <agraf@suse.de> wrote:
> +    env->reset_msr = (1ULL < MSR_SF);

I assume you mean "<<" rather than "<" here and below...

-- PMM
Alexander Graf - June 21, 2012, 7:04 p.m.
On 21.06.2012, at 20:09, Blue Swirl <blauwirbel@gmail.com> wrote:

> On Wed, Jun 20, 2012 at 8:11 PM, Alexander Graf <agraf@suse.de> wrote:
>> Some machines have MSR bits they reset with as enabled. Don't hardcode the
>> logic, but let the individual core implementations save their own reset
>> mask into an env variable.
>> 
>> Signed-off-by: Alexander Graf <agraf@suse.de>
>> ---
>>  target-ppc/cpu.h            |    1 +
>>  target-ppc/translate_init.c |   14 ++++++++------
>>  2 files changed, 9 insertions(+), 6 deletions(-)
>> 
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 652a35a..acf5816 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1043,6 +1043,7 @@ struct CPUPPCState {
>>  #if defined(TARGET_PPC64)
>>     struct ppc_segment_page_sizes sps;
>>  #endif
>> +    uint64_t reset_msr;
>> 
>>  #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
>>     target_phys_addr_t vpa;
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index 57027a2..efa05fc 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -6273,6 +6273,7 @@ static void init_proc_970 (CPUPPCState *env)
>>     env->slb_nr = 32;
>>  #endif
>>     init_excp_970(env);
>> +    env->reset_msr = (1ULL < MSR_SF);
> 
> The parenthesis are not necessary.

Already dropped this patch :).

Alex

Patch

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 652a35a..acf5816 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1043,6 +1043,7 @@  struct CPUPPCState {
 #if defined(TARGET_PPC64)
     struct ppc_segment_page_sizes sps;
 #endif
+    uint64_t reset_msr;
 
 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
     target_phys_addr_t vpa;
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 57027a2..efa05fc 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6273,6 +6273,7 @@  static void init_proc_970 (CPUPPCState *env)
     env->slb_nr = 32;
 #endif
     init_excp_970(env);
+    env->reset_msr = (1ULL < MSR_SF);
     env->dcache_line_size = 128;
     env->icache_line_size = 128;
     /* Allocate hardware IRQ controller */
@@ -6375,6 +6376,7 @@  static void init_proc_970FX (CPUPPCState *env)
     env->slb_nr = 64;
 #endif
     init_excp_970(env);
+    env->reset_msr = (1ULL < MSR_SF);
     env->dcache_line_size = 128;
     env->icache_line_size = 128;
     /* Allocate hardware IRQ controller */
@@ -6465,6 +6467,7 @@  static void init_proc_970GX (CPUPPCState *env)
     env->slb_nr = 32;
 #endif
     init_excp_970(env);
+    env->reset_msr = (1ULL < MSR_SF);
     env->dcache_line_size = 128;
     env->icache_line_size = 128;
     /* Allocate hardware IRQ controller */
@@ -6555,6 +6558,7 @@  static void init_proc_970MP (CPUPPCState *env)
     env->slb_nr = 32;
 #endif
     init_excp_970(env);
+    env->reset_msr = (1ULL < MSR_SF);
     env->dcache_line_size = 128;
     env->icache_line_size = 128;
     /* Allocate hardware IRQ controller */
@@ -6640,6 +6644,7 @@  static void init_proc_POWER7 (CPUPPCState *env)
     env->slb_nr = 32;
 #endif
     init_excp_POWER7(env);
+    env->reset_msr = (1ULL < MSR_SF);
     env->dcache_line_size = 128;
     env->icache_line_size = 128;
     /* Allocate hardware IRQ controller */
@@ -6686,6 +6691,7 @@  static void init_proc_620 (CPUPPCState *env)
     /* Memory management */
     gen_low_BATs(env);
     init_excp_620(env);
+    env->reset_msr = (1ULL < MSR_SF);
     env->dcache_line_size = 64;
     env->icache_line_size = 64;
     /* Allocate hardware IRQ controller */
@@ -9306,6 +9312,7 @@  static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
     env->nb_BATs = 0;
     env->nb_tlb = 0;
     env->nb_ways = 0;
+    env->reset_msr = 0;
     env->tlb_type = TLB_NONE;
 #endif
     /* Register SPR common to all PowerPC implementations */
@@ -10246,7 +10253,7 @@  static void ppc_cpu_reset(CPUState *s)
 
     pcc->parent_reset(s);
 
-    msr = (target_ulong)0;
+    msr = (target_ulong)env->reset_msr;
     if (0) {
         /* XXX: find a suitable condition to enable the hypervisor mode */
         msr |= (target_ulong)MSR_HVB;
@@ -10272,11 +10279,6 @@  static void ppc_cpu_reset(CPUState *s)
     }
 #endif
     env->msr = msr & env->msr_mask;
-#if defined(TARGET_PPC64)
-    if (env->mmu_model & POWERPC_MMU_64) {
-        env->msr |= (1ULL << MSR_SF);
-    }
-#endif
     hreg_compute_hflags(env);
     env->reserve_addr = (target_ulong)-1ULL;
     /* Be sure no exception or interrupt is pending */