Patchwork [i386] : Macroize with int iterators remaining insn patterns

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Submitter Uros Bizjak
Date June 20, 2012, 7:30 p.m.
Message ID <CAFULd4bpGnxvmMa1hYy040sjX3-nLjh8w_xfnoR8N0Z-wDOiYg@mail.gmail.com>
Download mbox | patch
Permalink /patch/166133/
State New
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Comments

Uros Bizjak - June 20, 2012, 7:30 p.m.
Hello!

2012-06-20  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (SINCOS): New int iterator.
	(sincos): New int attribute.
	(*<sincos>xf2_i387): Macroize insn from *{sin,cos}xf2_i387 using
	SINCOS int iterator.
	(*<sincos>_extend<mode>xf2_i387): Macroize insn from
	*{sin,cos}_extend<mode>xf2_i387 using SINCOS int iterator.

2012-06-20  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (RDFSGSBASE): New int iterator.
	(WRFSGSBASE): Ditto.
	(fsgs): New int attribute.
	(rd<fsgs>base<mode>): Macroize insn from rd<fsgs>base<mode> using
	RDFSGSBASE int iterator.
	(wr<fsgs>base<mode>): Macroize insn from wr<fsgs>base<mode> using
	WRFSGSBASE int iterator.

Bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32},
committed to mainline SVN.

Uros.

Patch

Index: i386.md
===================================================================
--- i386.md	(revision 188840)
+++ i386.md	(working copy)
@@ -13863,47 +13863,34 @@ 
   DONE;
 })
 
-(define_insn "*sinxf2_i387"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
-  "TARGET_USE_FANCY_MATH_387
-   && flag_unsafe_math_optimizations"
-  "fsin"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
+(define_int_iterator SINCOS
+	[UNSPEC_SIN
+	 UNSPEC_COS])
 
-(define_insn "*sin_extend<mode>xf2_i387"
-  [(set (match_operand:XF 0 "register_operand" "=f")
-	(unspec:XF [(float_extend:XF
-		      (match_operand:MODEF 1 "register_operand" "0"))]
-		   UNSPEC_SIN))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
-       || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-  "fsin"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "XF")])
+(define_int_attr sincos
+	[(UNSPEC_SIN "sin")
+	 (UNSPEC_COS "cos")])
 
-(define_insn "*cosxf2_i387"
+(define_insn "*<sincos>xf2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
-	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
+	(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+		   SINCOS))]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
-  "fcos"
+  "f<sincos>"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
-(define_insn "*cos_extend<mode>xf2_i387"
+(define_insn "*<sincos>_extend<mode>xf2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(unspec:XF [(float_extend:XF
 		      (match_operand:MODEF 1 "register_operand" "0"))]
-		   UNSPEC_COS))]
+		   SINCOS))]
   "TARGET_USE_FANCY_MATH_387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)
    && flag_unsafe_math_optimizations"
-  "fcos"
+  "f<sincos>"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")])
 
@@ -18087,38 +18074,36 @@ 
    (set (attr "length")
         (symbol_ref "ix86_attr_length_address_default (insn) + 9"))])
 
-(define_insn "rdfsbase<mode>"
-  [(set (match_operand:SWI48 0 "register_operand" "=r")
-	(unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDFSBASE))]
-  "TARGET_64BIT && TARGET_FSGSBASE"
-  "rdfsbase %0"
-  [(set_attr "type" "other")
-   (set_attr "prefix_extra" "2")])
+(define_int_iterator RDFSGSBASE
+	[UNSPECV_RDFSBASE
+	 UNSPECV_RDGSBASE])
 
-(define_insn "rdgsbase<mode>"
+(define_int_iterator WRFSGSBASE
+	[UNSPECV_WRFSBASE
+	 UNSPECV_WRGSBASE])
+
+(define_int_attr fsgs
+	[(UNSPECV_RDFSBASE "fs")
+	 (UNSPECV_RDGSBASE "gs")
+	 (UNSPECV_WRFSBASE "fs")
+	 (UNSPECV_WRGSBASE "gs")])
+
+(define_insn "rd<fsgs>base<mode>"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
-	(unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDGSBASE))]
+	(unspec_volatile:SWI48 [(const_int 0)] RDFSGSBASE))]
   "TARGET_64BIT && TARGET_FSGSBASE"
-  "rdgsbase %0"
+  "rd<fsgs>base\t%0"
   [(set_attr "type" "other")
    (set_attr "prefix_extra" "2")])
 
-(define_insn "wrfsbase<mode>"
+(define_insn "wr<fsgs>base<mode>"
   [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
-		    UNSPECV_WRFSBASE)]
+		    WRFSGSBASE)]
   "TARGET_64BIT && TARGET_FSGSBASE"
-  "wrfsbase %0"
+  "wr<fsgs>base\t%0"
   [(set_attr "type" "other")
    (set_attr "prefix_extra" "2")])
 
-(define_insn "wrgsbase<mode>"
-  [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
-		    UNSPECV_WRGSBASE)]
-  "TARGET_64BIT && TARGET_FSGSBASE"
-  "wrgsbase %0"
-  [(set_attr "type" "other")
-   (set_attr "prefix_extra" "2")])
-
 (define_insn "rdrand<mode>_1"
   [(set (match_operand:SWI248 0 "register_operand" "=r")
 	(unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))