From patchwork Wed Jun 20 12:26:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 166105 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B8714B6FD5 for ; Thu, 21 Jun 2012 00:56:21 +1000 (EST) Received: from localhost ([::1]:59208 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKTr-0006k1-IH for incoming@patchwork.ozlabs.org; Wed, 20 Jun 2012 08:57:55 -0400 Received: from eggs.gnu.org ([208.118.235.92]:39796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKSx-0004ez-La for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:57:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ShKSq-00028Z-Rm for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:56:59 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:59525) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKSq-00025V-J3 for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:56:52 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1ShK0I-0004Kl-1E; Wed, 20 Jun 2012 13:27:22 +0100 From: Peter Maydell To: Blue Swirl Date: Wed, 20 Jun 2012 13:26:56 +0100 Message-Id: <1340195241-16620-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> References: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: qemu-devel@nongnu.org, Anthony Liguori , Paul Brook Subject: [Qemu-devel] [PATCH 08/33] target-arm: Convert debug registers to cp_reginfo X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme. Signed-off-by: Peter Maydell --- target-arm/helper.c | 25 +++++++++++++++++++++++++ target-arm/translate.c | 28 ---------------------------- 2 files changed, 25 insertions(+), 28 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index f7c9a3a..a750637 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -56,6 +56,27 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +static const ARMCPRegInfo cp_reginfo[] = { + /* DBGDIDR: just RAZ. In particular this means the "debug architecture + * version" bits will read as a reserved value, which should cause + * Linux to not try to use the debug hardware. + */ + { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo v7_cp_reginfo[] = { + /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped + * debug components + */ + { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -65,6 +86,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) return; } + define_arm_cp_regs(cpu, cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V7)) { + define_arm_cp_regs(cpu, v7_cp_reginfo); + } } ARMCPU *cpu_arm_init(const char *cpu_model) diff --git a/target-arm/translate.c b/target-arm/translate.c index 75e464d..d9fa431 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6364,34 +6364,6 @@ static int disas_cp14_read(CPUARMState * env, DisasContext *s, uint32_t insn) int rt = (insn >> 12) & 0xf; TCGv tmp; - /* Minimal set of debug registers, since we don't support debug */ - if (op1 == 0 && crn == 0 && op2 == 0) { - switch (crm) { - case 0: - /* DBGDIDR: just RAZ. In particular this means the - * "debug architecture version" bits will read as - * a reserved value, which should cause Linux to - * not try to use the debug hardware. - */ - tmp = tcg_const_i32(0); - store_reg(s, rt, tmp); - return 0; - case 1: - case 2: - /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we - * don't implement memory mapped debug components - */ - if (ENABLE_ARCH_7) { - tmp = tcg_const_i32(0); - store_reg(s, rt, tmp); - return 0; - } - break; - default: - break; - } - } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { /* TEECR */