From patchwork Wed Jun 20 12:27:20 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 166055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0462DB6FD5 for ; Wed, 20 Jun 2012 22:57:11 +1000 (EST) Received: from localhost ([::1]:55068 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKT6-0004Tt-OU for incoming@patchwork.ozlabs.org; Wed, 20 Jun 2012 08:57:08 -0400 Received: from eggs.gnu.org ([208.118.235.92]:39688) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKSk-0004Eg-Of for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:56:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ShKSh-00026D-1r for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:56:46 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:59525) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ShKSg-00025V-NZ for qemu-devel@nongnu.org; Wed, 20 Jun 2012 08:56:42 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1ShK0K-0004Mp-9R; Wed, 20 Jun 2012 13:27:24 +0100 From: Peter Maydell To: Blue Swirl Date: Wed, 20 Jun 2012 13:27:20 +0100 Message-Id: <1340195241-16620-33-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> References: <1340195241-16620-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: qemu-devel@nongnu.org, Anthony Liguori , Paul Brook Subject: [Qemu-devel] [PATCH 32/33] target-arm: Remove remaining old cp15 infrastructure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: Peter Maydell --- target-arm/helper.c | 39 ------------------------------- target-arm/helper.h | 3 -- target-arm/translate.c | 59 +----------------------------------------------- 3 files changed, 1 insertions(+), 100 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 10d4635..2309923 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1441,16 +1441,6 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, return 1; } -void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) -{ - cpu_abort(env, "cp15 insn %08x\n", insn); -} - -uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) -{ - cpu_abort(env, "cp15 insn %08x\n", insn); -} - /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { @@ -2177,35 +2167,6 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr) return phys_addr; } -void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) -{ - int op1; - int op2; - int crm; - - op1 = (insn >> 21) & 7; - op2 = (insn >> 5) & 7; - crm = insn & 0xf; - /* ??? For debugging only. Should raise illegal instruction exception. */ - cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n", - (insn >> 16) & 0xf, crm, op1, op2); -} - -uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) -{ - int op1; - int op2; - int crm; - - op1 = (insn >> 21) & 7; - op2 = (insn >> 5) & 7; - crm = insn & 0xf; - /* ??? For debugging only. Should raise illegal instruction exception. */ - cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n", - (insn >> 16) & 0xf, crm, op1, op2); - return 0; -} - void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) { if ((env->uncached_cpsr & CPSR_M) == mode) { diff --git a/target-arm/helper.h b/target-arm/helper.h index a0034ae..21e9cfe 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -59,9 +59,6 @@ DEF_HELPER_0(cpsr_read, i32) DEF_HELPER_3(v7m_msr, void, env, i32, i32) DEF_HELPER_2(v7m_mrs, i32, env, i32) -DEF_HELPER_3(set_cp15, void, env, i32, i32) -DEF_HELPER_2(get_cp15, i32, env, i32) - DEF_HELPER_3(set_cp_reg, void, env, ptr, i32) DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) diff --git a/target-arm/translate.c b/target-arm/translate.c index fcdc9d3..a2a0ecd 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2439,55 +2439,6 @@ static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn) return 1; } -/* Disassemble system coprocessor (cp15) instruction. Return nonzero if - instruction is not defined. */ -static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) -{ - uint32_t rd; - TCGv tmp, tmp2; - - /* M profile cores use memory mapped registers instead of cp15. */ - if (arm_feature(env, ARM_FEATURE_M)) - return 1; - - if ((insn & (1 << 25)) == 0) { - return 1; - } - if ((insn & (1 << 4)) == 0) { - /* cdp */ - return 1; - } - - if (IS_USER(s)) { - return 1; - } - - rd = (insn >> 12) & 0xf; - - tmp2 = tcg_const_i32(insn); - if (insn & ARM_CP_RW_BIT) { - tmp = tcg_temp_new_i32(); - gen_helper_get_cp15(tmp, cpu_env, tmp2); - /* If the destination register is r15 then sets condition codes. */ - if (rd != 15) - store_reg(s, rd, tmp); - else - tcg_temp_free_i32(tmp); - } else { - tmp = load_reg(s, rd); - gen_helper_set_cp15(cpu_env, tmp2, tmp); - tcg_temp_free_i32(tmp); - /* Normally we would always end the TB here, but Linux - * arch/arm/mach-pxa/sleep.S expects two instructions following - * an MMU enable to execute from cache. Imitate this behaviour. */ - if (!arm_feature(env, ARM_FEATURE_XSCALE) || - (insn & 0x0fff0fff) != 0x0e010f10) - gen_lookup_tb(s); - } - tcg_temp_free_i32(tmp2); - return 0; -} - #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n)) #define VFP_SREG(insn, bigbit, smallbit) \ ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) @@ -6388,15 +6339,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) return 0; } - /* Fallback code: handle coprocessor registers not yet converted - * to ARMCPRegInfo. - */ - switch (cpnum) { - case 15: - return disas_cp15_insn (env, s, insn); - default: - return 1; - } + return 1; }