From patchwork Tue Jun 19 13:31:07 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 165727 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 67AD9B700A for ; Tue, 19 Jun 2012 23:57:05 +1000 (EST) Received: from localhost ([::1]:51380 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgyvX-0006bq-AU for incoming@patchwork.ozlabs.org; Tue, 19 Jun 2012 09:57:03 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52930) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgyvD-0006O2-JL for qemu-devel@nongnu.org; Tue, 19 Jun 2012 09:56:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Sgyv7-00072a-22 for qemu-devel@nongnu.org; Tue, 19 Jun 2012 09:56:43 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:44844) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Sgyv6-00072F-Q4 for qemu-devel@nongnu.org; Tue, 19 Jun 2012 09:56:36 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SgyWY-0003sE-OY; Tue, 19 Jun 2012 14:31:14 +0100 From: Peter Maydell To: Blue Swirl Date: Tue, 19 Jun 2012 14:31:07 +0100 Message-Id: <1340112673-14846-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1340112673-14846-1-git-send-email-peter.maydell@linaro.org> References: <1340112673-14846-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Anthony Liguori , qemu-devel@nongnu.org, Paul Brook Subject: [Qemu-devel] [PATCH 10/16] hw/arm_gic: Move CPU interface memory region setup into arm_gic_init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Remove more NVIC ifdefs by moving the code to setup the CPU interface memory regions into the GIC specific arm_gic_init() function rather than the gic_init() function. Rename the latter to more closely reflect what it's now actually doing. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 26 +++++++++++++------------- hw/armv7m_nvic.c | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index c288bc5..ad5ab3c 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -812,7 +812,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static void gic_init(gic_state *s, int num_irq) +static void gic_init_irqs_and_distributor(gic_state *s, int num_irq) { int i; @@ -850,7 +850,19 @@ static void gic_init(gic_state *s, int num_irq) sysbus_init_irq(&s->busdev, &s->parent_irq[i]); } memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000); + + register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s); +} + #ifndef NVIC + +static int arm_gic_init(SysBusDevice *dev) +{ + /* Device instance init function for the GIC sysbus device */ + int i; + gic_state *s = FROM_SYSBUS(gic_state, dev); + gic_init_irqs_and_distributor(s, s->num_irq); + /* Memory regions for the CPU interfaces (NVIC doesn't have these): * a region for "CPU interface for this core", then a region for * "CPU interface for core 0", "for core 1", ... @@ -866,19 +878,7 @@ static void gic_init(gic_state *s, int num_irq) memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i], "gic_cpu", 0x100); } -#endif - - register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s); -} - -#ifndef NVIC -static int arm_gic_init(SysBusDevice *dev) -{ - /* Device instance init function for the GIC sysbus device */ - int i; - gic_state *s = FROM_SYSBUS(gic_state, dev); - gic_init(s, s->num_irq); /* Distributor */ sysbus_init_mmio(dev, &s->iomem); /* cpu interfaces (one for "current cpu" plus one per cpu) */ diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 4c130f1..031a7fd 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -449,7 +449,7 @@ static int armv7m_nvic_init(SysBusDevice *dev) s->gic.num_cpu = 1; /* Tell the common code we're an NVIC */ s->gic.revision = 0xffffffff; - gic_init(&s->gic, s->num_irq); + gic_init_irqs_and_distributor(&s->gic, s->num_irq); /* The NVIC and system controller register area looks like this: * 0..0xff : system control registers, including systick * 0x100..0xcff : GIC-like registers