Patchwork [arm] Remove obsolete FPA support (7/n): Tidy up attributes

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Submitter Richard Earnshaw
Date June 19, 2012, 1:43 p.m.
Message ID <4FE081EB.7030407@arm.com>
Download mbox | patch
Permalink /patch/165725/
State New
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Comments

Richard Earnshaw - June 19, 2012, 1:43 p.m.
This patch cleans up some more of the resulting fall-out from removing
the FPA and maverick co-processors.  In particular it covers:

- Removing the redundant states from the type attributes
- Removing some now redundant UNSPEC values.
- Removing some state from the generic scheduler description that is now
no-longer needed.

Tested on arm-eabi and installed on trunk.

	* arm.md (enum unspec): Delete UNSPEC_SIN and UNSPEC_COS.
	(attr type): Remove fmul, ffmul, farith, ffarith, float_em
	f_fpa_load, f_fpa_store, f_mem_r, r_mem_f.
	(attr write_conflict, attr core_cycles): Update.
	* arm-generic.md (r_mem_f_wbuf): Delete reservation.

R.

Patch

Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md	(revision 188771)
+++ config/arm/arm.md	(working copy)
@@ -65,12 +65,6 @@  (define_constants
 ;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
 
 (define_c_enum "unspec" [
-  UNSPEC_SIN            ; `sin' operation (MODE_FLOAT):
-                        ;   operand 0 is the result,
-                        ;   operand 1 the parameter.
-  UNPSEC_COS            ; `cos' operation (MODE_FLOAT):
-                        ;   operand 0 is the result,
-                        ;   operand 1 the parameter.
   UNSPEC_PUSH_MULT      ; `push multiple' operation:
                         ;   operand 0 is the first register,
                         ;   subsequent registers are in parallel (use ...)
@@ -321,21 +315,11 @@  (define_attr "insn"
 ; float		a floating point arithmetic operation (subject to expansion)
 ; fdivd		DFmode floating point division
 ; fdivs		SFmode floating point division
-; fmul		Floating point multiply
-; ffmul		Fast floating point multiply
-; farith	Floating point arithmetic (4 cycle)
-; ffarith	Fast floating point arithmetic (2 cycle)
-; float_em	a floating point arithmetic operation that is normally emulated
-;		even on a machine with an fpa.
-; f_fpa_load	a floating point load from memory. Only for the FPA.
-; f_fpa_store	a floating point store to memory. Only for the FPA.
 ; f_load[sd]	A single/double load from memory. Used for VFP unit.
 ; f_store[sd]	A single/double store to memory. Used for VFP unit.
 ; f_flag	a transfer of co-processor flags to the CPSR
-; f_mem_r	a transfer of a floating point register to a real reg via mem
-; r_mem_f	the reverse of f_mem_r
-; f_2_r		fast transfer float to arm (no memory needed)
-; r_2_f		fast transfer arm to float
+; f_2_r		transfer float to core (no memory needed)
+; r_2_f		transfer core to float
 ; f_cvt		convert floating<->integral
 ; branch	a branch
 ; call		a subroutine call
@@ -351,18 +335,59 @@  (define_attr "insn"
 ;
 
 (define_attr "type"
-	"alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,fmuls,fmuld,fmacs,fmacd,ffmul,farith,ffarith,f_flag,float_em,f_fpa_load,f_fpa_store,f_loads,f_loadd,f_stores,f_stored,f_mem_r,r_mem_f,f_2_r,r_2_f,f_cvt,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,fconsts,fconstd,fadds,faddd,ffariths,ffarithd,fcmps,fcmpd,fcpys"
-	(if_then_else 
-	 (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
-	 (const_string "mult")
-	 (const_string "alu")))
+ "alu,\
+  alu_shift,\
+  alu_shift_reg,\
+  mult,\
+  block,\
+  float,\
+  fdivd,\
+  fdivs,\
+  fmuls,\
+  fmuld,\
+  fmacs,\
+  fmacd,\
+  f_flag,\
+  f_loads,\
+  f_loadd,\
+  f_stores,\
+  f_stored,\
+  f_2_r,\
+  r_2_f,\
+  f_cvt,\
+  branch,\
+  call,\
+  load_byte,\
+  load1,\
+  load2,\
+  load3,\
+  load4,\
+  store1,\
+  store2,\
+  store3,\
+  store4,\
+  fconsts,\
+  fconstd,\
+  fadds,\
+  faddd,\
+  ffariths,\
+  ffarithd,\
+  fcmps,\
+  fcmpd,\
+  fcpys"
+ (if_then_else 
+    (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,\
+	     	     umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
+    (const_string "mult")
+    (const_string "alu")))
 
 ; Is this an (integer side) multiply with a 64-bit result?
 (define_attr "mul64" "no,yes"
-	     (if_then_else
-	       (eq_attr "insn" "smlalxy,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
-	       (const_string "yes")
-	       (const_string "no")))
+  (if_then_else
+    (eq_attr "insn"
+     "smlalxy,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals")
+    (const_string "yes")
+    (const_string "no")))
 
 ; wtype for WMMX insn scheduling purposes.
 (define_attr "wtype"
@@ -486,7 +511,7 @@  (define_attr "model_wbuf" "no,yes" (cons
 ; to stall the processor.  Used with model_wbuf above.
 (define_attr "write_conflict" "no,yes"
   (if_then_else (eq_attr "type"
-		 "block,float_em,f_fpa_load,f_fpa_store,f_mem_r,r_mem_f,call,load1")
+		 "block,call,load1")
 		(const_string "yes")
 		(const_string "no")))
 
@@ -494,7 +519,7 @@  (define_attr "write_conflict" "no,yes"
 ; than one on the main cpu execution unit.
 (define_attr "core_cycles" "single,multi"
   (if_then_else (eq_attr "type"
-		 "alu,alu_shift,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith")
+		 "alu,alu_shift,float,fdivd,fdivs")
 		(const_string "single")
 	        (const_string "multi")))
 
Index: config/arm/arm-generic.md
===================================================================
--- config/arm/arm-generic.md	(revision 188771)
+++ config/arm/arm-generic.md	(working copy)
@@ -38,20 +38,12 @@  (define_cpu_unit "write_buf" "arm")
 ;
 ; The write_blockage unit models (partially), the fact that reads will stall
 ; until the write buffer empties.
-; The f_mem_r and r_mem_f could also block, but they are to the stack,
-; so we don't model them here
 (define_cpu_unit "write_blockage" "arm")
 
 ;; Core
 ;
 (define_cpu_unit "core" "arm")
 
-(define_insn_reservation "r_mem_f_wbuf" 5
-  (and (eq_attr "generic_sched" "yes")
-       (and (eq_attr "model_wbuf" "yes")
-	    (eq_attr "type" "r_mem_f")))
-  "core+write_buf*3")
-
 (define_insn_reservation "store_wbuf" 5
   (and (eq_attr "generic_sched" "yes")
        (and (eq_attr "model_wbuf" "yes")