From patchwork Mon Jun 18 16:35:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 165563 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 166DDB7048 for ; Tue, 19 Jun 2012 03:52:26 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 03D7928154; Mon, 18 Jun 2012 19:51:04 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EhKSnSSdhocX; Mon, 18 Jun 2012 19:51:03 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D594B28155; Mon, 18 Jun 2012 19:48:40 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 41795280B1 for ; Mon, 18 Jun 2012 18:36:07 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jD1PC-A+2tzE for ; Mon, 18 Jun 2012 18:36:07 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pz0-f44.google.com (mail-pz0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id C7E1B280C1 for ; Mon, 18 Jun 2012 18:36:06 +0200 (CEST) Received: by dacx6 with SMTP id x6so6711724dac.3 for ; Mon, 18 Jun 2012 09:36:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=mFz96BeNrt9SxGEDEAhiO1EQ97vWJItmjgnBiR4cwbU=; b=dYMLj+2MRTc8AfBA3sNOTGE00kHvn2kyAtqQGHlqp/kIexvzzUm7ue40fsRfGTWihy BUr6uMqevLZnRVoIp0CmxbBzyUAQ7/Dgol6+ryXsTs1RIi3EMabGD4ZSR9lMj6jOe4oC oDpVAmZ9xUT5XknNdUVDyLnWe0hGOPiK4fX3nfuyc0Oaey0SywG9OwTwIuxFGt+8TxoV ARAk9mHxsEoWvmowXVM1Nl015vCH2Y2F/IHdhJqYy0Clitg7zNT3MviRwUpGmNSQXRFi Hkl7m+GmHLNCFuv4Xd0pm/sDDCITV2j9Tuhs583Bt1qkkxFLa/rjmT8IJWa6c3+oQuZG tvDA== Received: by 10.68.138.169 with SMTP id qr9mr53735771pbb.27.1340037364945; Mon, 18 Jun 2012 09:36:04 -0700 (PDT) Received: from localhost.localdomain (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPS id os9sm24389049pbb.62.2012.06.18.09.36.03 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:36:04 -0700 (PDT) From: mathieu.poirier@linaro.org To: u-boot@lists.denx.de Date: Mon, 18 Jun 2012 10:35:43 -0600 Message-Id: <1340037344-2497-11-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1340037344-2497-1-git-send-email-mathieu.poirier@linaro.org> References: <1340037344-2497-1-git-send-email-mathieu.poirier@linaro.org> X-Gm-Message-State: ALoCoQkr60f4rELZpZmZGkgUilqa9ZoLWvak4jSrkkEi0B8hfkpoyte36nYgJZFiesMwnk0Qwgdi X-Mailman-Approved-At: Mon, 18 Jun 2012 19:48:03 +0200 Cc: lee.jones@linaro.org, patches@linaro.org Subject: [U-Boot] [PATCH 10/11] armv7: Adding cpu specific cache managmenent X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: "Mathieu J. Poirier" Some CPU (i.e u8500) need more cache management before launching the Linux kernel. Signed-off-by: Mathieu Poirier Signed-off-by: John Rigby --- arch/arm/cpu/armv7/cpu.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index c6fa8ef..53c8baf 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -44,6 +44,10 @@ void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3) void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) __attribute__((weak, alias("save_boot_params_default"))); +void __cpu_cache_management(void){} +void cpu_cache_management(void) __attribute__((weak, + alias("__cpu_cache_management"))); + int cleanup_before_linux(void) { /* @@ -81,5 +85,10 @@ int cleanup_before_linux(void) */ invalidate_dcache_all(); + /* + * Some CPU need more cache attention before starting the kernel. + */ + cpu_cache_management(); + return 0; }