From patchwork Mon Jun 18 16:25:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 165546 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2A28CB6FF7 for ; Tue, 19 Jun 2012 03:49:20 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A9FA2280D7; Mon, 18 Jun 2012 19:49:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Q2TaQZBCrFnn; Mon, 18 Jun 2012 19:49:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0B743280D8; Mon, 18 Jun 2012 19:48:13 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 364AC280A6 for ; Mon, 18 Jun 2012 18:25:53 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id x9p7Pte+26GB for ; Mon, 18 Jun 2012 18:25:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pz0-f44.google.com (mail-pz0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id 0F483280AB for ; Mon, 18 Jun 2012 18:25:50 +0200 (CEST) Received: by dacx6 with SMTP id x6so6699831dac.3 for ; Mon, 18 Jun 2012 09:25:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=I9by1XGeOi/3BXMo5KEBCWer0XQOm8/LZaleu9U1Cdo=; b=B5ze19IuDJc5HQl+wMbO81rhBbLPArO61wyFe87CLqZVpcZQw0hzcoR58ulueaESCm URGpxhrYKCr4/RmxhA3pYeNpaXhq5JOho9dmebUqgcmYotstZsa31/rVCJG58A0TZ8YY rGhOX1lrkaEHns2AIvd1TqLIEF+ejqXeBMcGqQcJPY6CyELl65rc4gdZmjhi0Makg1Vt YRDJZEaqH4R5IZn7juZxkC/7F4jjGTGCP7lLYRvNFTA3gvf41VZrGgNwL+cGtOtslqCK iO1KljnjgCxrTVbuypCbz7oB41at7VhfCmLnY9hwgbou/oeIwJD4a6voBwgFaaucs++8 fgrg== Received: by 10.68.231.229 with SMTP id tj5mr33749924pbc.39.1340036748579; Mon, 18 Jun 2012 09:25:48 -0700 (PDT) Received: from localhost.localdomain (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPS id mq8sm51844pbb.64.2012.06.18.09.25.47 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:25:48 -0700 (PDT) From: mathieu.poirier@linaro.org To: u-boot@lists.denx.de Date: Mon, 18 Jun 2012 10:25:29 -0600 Message-Id: <1340036736-2436-5-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1340036736-2436-1-git-send-email-mathieu.poirier@linaro.org> References: <1340036736-2436-1-git-send-email-mathieu.poirier@linaro.org> X-Gm-Message-State: ALoCoQmKtsZ3nQn516XKkNfRd8jMZYvL6979IXOZ7RXvi2m64D+Bpv0X+GCFtu5b9FqZXT/jGgzL X-Mailman-Approved-At: Mon, 18 Jun 2012 19:48:03 +0200 Cc: lee.jones@linaro.org, patches@linaro.org Subject: [U-Boot] [PATCH 04/11] snowball: Adding CPU clock initialisation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: "Mathieu J. Poirier" Signed-off-by: Mathieu Poirier Signed-off-by: John Rigby --- arch/arm/cpu/armv7/u8500/clock.c | 34 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/u8500/cpu.c | 2 + arch/arm/include/asm/arch-u8500/clock.h | 5 +--- 3 files changed, 37 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/clock.c b/arch/arm/cpu/armv7/u8500/clock.c index 9e3b873..fcfd61a 100644 --- a/arch/arm/cpu/armv7/u8500/clock.c +++ b/arch/arm/cpu/armv7/u8500/clock.c @@ -54,3 +54,37 @@ void u8500_clock_enable(int periph, int cluster, int kern) if (cluster != -1) writel(1 << cluster, &clkrst->pcken); } + +void db8500_clocks_init(void) +{ + /* + * Enable all clocks. This is u-boot, we can enable it all. There is no + * powersave in u-boot. + */ + + u8500_clock_enable(1, 9, -1); /* GPIO0 */ + u8500_clock_enable(2, 11, -1);/* GPIO1 */ + u8500_clock_enable(3, 8, -1); /* GPIO2 */ + u8500_clock_enable(5, 1, -1); /* GPIO3 */ + u8500_clock_enable(3, 6, 6); /* UART2 */ + u8500_clock_enable(3, 3, 3); /* I2C0 */ + u8500_clock_enable(1, 5, 5); /* SDI0 */ + u8500_clock_enable(2, 4, 2); /* SDI4 */ + u8500_clock_enable(6, 6, -1); /* MTU0 */ + u8500_clock_enable(3, 4, 4); /* SDI2 */ + + /* + * Enabling clocks for all devices which are AMBA devices in the + * kernel. Otherwise they will not get probe()'d because the + * peripheral ID register will not be powered. + */ + + /* XXX: some of these differ between ED/V1 */ + + u8500_clock_enable(1, 1, 1); /* UART1 */ + u8500_clock_enable(1, 0, 0); /* UART0 */ + u8500_clock_enable(3, 2, 2); /* SSP1 */ + u8500_clock_enable(3, 1, 1); /* SSP0 */ + u8500_clock_enable(2, 8, -1); /* SPI0 */ + u8500_clock_enable(2, 5, 3); /* MSP2 */ +} diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index 04f4b19..fece201 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -27,6 +27,7 @@ #include #include #include +#include #ifdef CONFIG_ARCH_CPU_INIT /* @@ -35,6 +36,7 @@ int arch_cpu_init(void) { db8500_prcmu_init(); + db8500_clocks_init(); return 0; } diff --git a/arch/arm/include/asm/arch-u8500/clock.h b/arch/arm/include/asm/arch-u8500/clock.h index b00ab0d..2a14784 100644 --- a/arch/arm/include/asm/arch-u8500/clock.h +++ b/arch/arm/include/asm/arch-u8500/clock.h @@ -64,9 +64,6 @@ struct prcmu { extern void u8500_clock_enable(int periph, int kern, int cluster); -static inline void u8500_prcmu_enable(unsigned int *reg) -{ - writel(readl(reg) | (1 << 8), reg); -} +void db8500_clocks_init(void); #endif /* __ASM_ARCH_CLOCK */