From patchwork Mon Jun 18 01:02:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 165378 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5F6D0B707C for ; Mon, 18 Jun 2012 12:05:46 +1000 (EST) Received: from localhost ([::1]:36948 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgRLc-0003fV-6e for incoming@patchwork.ozlabs.org; Sun, 17 Jun 2012 22:05:44 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50201) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOM-0002Rn-LP for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SgQOK-00056p-SJ for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:30 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:43016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOK-0004jq-JA for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:28 -0400 Received: by mail-pz0-f45.google.com with SMTP id n2so5607657dad.4 for ; Sun, 17 Jun 2012 18:04:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=xUbLSCengl2d+CXhud3yRMEQkVAlVvBtUcbB7vQ7Zwc=; b=rDM4UjIsXCSwTE3YCQt3PYTWVDCvhIIefVZdA0tTbQoYNe8UlyrOC9t6mz7DwWrdJO ERXlO/3ASj8cXm+Q7BHpywd84f1M0sokMHrkab+zyc0rvlAqcrD5P18+3WqhNKGC/1va 76c4zb5G5e+F+Kq930g1+ZbV9ZpRxCcxSpXNa8sIRx1VT6JiWzH86RzRBfUSyeFlHmfl pfnsdBQBtFB6qBEzRB5F5QQJISz9aoXl9J/b7a6JTNYLn4/3djpWu9aewW5JC6GP6Drl trqE7nUc6FqWL0NiaQxA90p9m3JpMtVPmCYAvSRL2z7vDBAfzY6oZX836mAqduC6xyuv amkQ== Received: by 10.68.223.198 with SMTP id qw6mr29324372pbc.94.1339981467669; Sun, 17 Jun 2012 18:04:27 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id wk3sm21909016pbc.21.2012.06.17.18.04.24 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 17 Jun 2012 18:04:26 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2012 09:02:58 +0800 Message-Id: <1339981384-9117-11-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1339981384-9117-1-git-send-email-proljc@gmail.com> References: <1339981384-9117-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH v5 10/16] target-or32: Add timer support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add OpenRISC timer support. Signed-off-by: Jia Liu --- hw/openrisc_timer.c | 130 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/hw/openrisc_timer.c b/hw/openrisc_timer.c index df384f6..25cde1a 100644 --- a/hw/openrisc_timer.c +++ b/hw/openrisc_timer.c @@ -22,9 +22,139 @@ #include "openrisc_cpudev.h" #include "qemu-timer.h" +#define TIMER_FREQ (20 * 1000 * 1000) /* 20MHz */ + +/* The time when TTCR changes */ +static uint64_t last_clk; +static int is_counting; + +/* Timer Mode */ +enum { + TIMER_NONE = (0 << 30), + TIMER_INTR = (1 << 30), + TIMER_SHOT = (2 << 30), + TIMER_CONT = (3 << 30), +}; + /* Reset Timer */ void cpu_openrisc_timer_reset(CPUOpenRISCState *env) { env->ttmr = 0x00000000; env->ttcr = 0x00000000; } + +static void count_update(CPUOpenRISCState *env) +{ + uint64_t now, next; + uint32_t wait; + + now = qemu_get_clock_ns(vm_clock); + if (!is_counting) { + qemu_del_timer(env->timer); + last_clk = now; + return; + } + + env->ttcr += (uint32_t)muldiv64(now - last_clk, TIMER_FREQ, + get_ticks_per_sec()); + last_clk = now; + + if ((env->ttmr & TTMR_TP) <= (env->ttcr & TTMR_TP)) { + wait = TTMR_TP - (env->ttcr & TTMR_TP) + 1; + wait += env->ttmr & TTMR_TP; + } else { + wait = (env->ttmr & TTMR_TP) - (env->ttcr & TTMR_TP); + } + + next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ); + qemu_mod_timer(env->timer, next); +} + +static void count_start(CPUOpenRISCState *env) +{ + is_counting = 1; + count_update(env); +} + +static void count_stop(CPUOpenRISCState *env) +{ + is_counting = 0; + count_update(env); +} + +uint32_t cpu_openrisc_get_count(CPUOpenRISCState *env) +{ + count_update(env); + return env->ttcr; +} + +void cpu_openrisc_store_count(CPUOpenRISCState *env, uint32_t count) +{ + /* Store new count register */ + env->ttcr = count; + if (env->ttmr & TIMER_NONE) { + return; + } + count_start(env); +} + +void cpu_openrisc_store_compare(CPUOpenRISCState *env, uint32_t value) +{ + int ip = env->ttmr & TTMR_IP; + + if (value & TTMR_IP) { /* Keep IP bit */ + env->ttmr = (value & ~TTMR_IP) + ip; + } else { /* Clear IP bit */ + env->ttmr = value & ~TTMR_IP; + env->interrupt_request &= ~CPU_INTERRUPT_TIMER; + } + count_update(env); + + switch (env->ttmr & TTMR_M) { + case TIMER_NONE: + count_stop(env); + break; + case TIMER_INTR: + count_start(env); + break; + case TIMER_SHOT: + count_start(env); + break; + case TIMER_CONT: + count_start(env); + break; + } +} + +static void openrisc_timer_cb(void *opaque) +{ + CPUOpenRISCState *env = opaque; + + if ((env->ttmr & TTMR_IE) && + qemu_timer_expired(env->timer, qemu_get_clock_ns(vm_clock))) { + env->ttmr |= TTMR_IP; + env->interrupt_request |= CPU_INTERRUPT_TIMER; + } + + switch (env->ttmr & TTMR_M) { + case TIMER_NONE: + break; + case TIMER_INTR: + env->ttcr = 0; + count_start(env); + break; + case TIMER_SHOT: + count_stop(env); + break; + case TIMER_CONT: + count_start(env); + break; + } +} + +void cpu_openrisc_clock_init(CPUOpenRISCState *env) +{ + env->timer = qemu_new_timer_ns(vm_clock, &openrisc_timer_cb, env); + env->ttmr = 0; + env->ttcr = 0; +}