Patchwork [v5,10/16] target-or32: Add timer support

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Submitter Jia Liu
Date June 18, 2012, 1:02 a.m.
Message ID <1339981384-9117-11-git-send-email-proljc@gmail.com>
Download mbox | patch
Permalink /patch/165378/
State New
Headers show

Comments

Jia Liu - June 18, 2012, 1:02 a.m.
Add OpenRISC timer support.

Signed-off-by: Jia Liu <proljc@gmail.com>
---
 hw/openrisc_timer.c |  130 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 130 insertions(+)

Patch

diff --git a/hw/openrisc_timer.c b/hw/openrisc_timer.c
index df384f6..25cde1a 100644
--- a/hw/openrisc_timer.c
+++ b/hw/openrisc_timer.c
@@ -22,9 +22,139 @@ 
 #include "openrisc_cpudev.h"
 #include "qemu-timer.h"
 
+#define TIMER_FREQ    (20 * 1000 * 1000)    /* 20MHz */
+
+/* The time when TTCR changes */
+static uint64_t last_clk;
+static int is_counting;
+
+/* Timer Mode */
+enum {
+    TIMER_NONE = (0 << 30),
+    TIMER_INTR = (1 << 30),
+    TIMER_SHOT = (2 << 30),
+    TIMER_CONT = (3 << 30),
+};
+
 /* Reset Timer */
 void cpu_openrisc_timer_reset(CPUOpenRISCState *env)
 {
     env->ttmr = 0x00000000;
     env->ttcr = 0x00000000;
 }
+
+static void count_update(CPUOpenRISCState *env)
+{
+    uint64_t now, next;
+    uint32_t wait;
+
+    now = qemu_get_clock_ns(vm_clock);
+    if (!is_counting) {
+        qemu_del_timer(env->timer);
+        last_clk = now;
+        return;
+    }
+
+    env->ttcr += (uint32_t)muldiv64(now - last_clk, TIMER_FREQ,
+                                    get_ticks_per_sec());
+    last_clk = now;
+
+    if ((env->ttmr & TTMR_TP) <= (env->ttcr & TTMR_TP)) {
+        wait = TTMR_TP - (env->ttcr & TTMR_TP) + 1;
+        wait += env->ttmr & TTMR_TP;
+    } else {
+        wait = (env->ttmr & TTMR_TP) - (env->ttcr & TTMR_TP);
+    }
+
+    next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
+    qemu_mod_timer(env->timer, next);
+}
+
+static void count_start(CPUOpenRISCState *env)
+{
+    is_counting = 1;
+    count_update(env);
+}
+
+static void count_stop(CPUOpenRISCState *env)
+{
+    is_counting = 0;
+    count_update(env);
+}
+
+uint32_t cpu_openrisc_get_count(CPUOpenRISCState *env)
+{
+    count_update(env);
+    return env->ttcr;
+}
+
+void cpu_openrisc_store_count(CPUOpenRISCState *env, uint32_t count)
+{
+    /* Store new count register */
+    env->ttcr = count;
+    if (env->ttmr & TIMER_NONE) {
+        return;
+    }
+    count_start(env);
+}
+
+void cpu_openrisc_store_compare(CPUOpenRISCState *env, uint32_t value)
+{
+    int ip = env->ttmr & TTMR_IP;
+
+    if (value & TTMR_IP) { /* Keep IP bit */
+        env->ttmr = (value & ~TTMR_IP) + ip;
+    } else {               /* Clear IP bit */
+        env->ttmr = value & ~TTMR_IP;
+        env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
+    }
+    count_update(env);
+
+    switch (env->ttmr & TTMR_M) {
+    case TIMER_NONE:
+        count_stop(env);
+        break;
+    case TIMER_INTR:
+        count_start(env);
+        break;
+    case TIMER_SHOT:
+        count_start(env);
+        break;
+    case TIMER_CONT:
+        count_start(env);
+        break;
+    }
+}
+
+static void openrisc_timer_cb(void *opaque)
+{
+    CPUOpenRISCState *env = opaque;
+
+    if ((env->ttmr & TTMR_IE) &&
+         qemu_timer_expired(env->timer, qemu_get_clock_ns(vm_clock))) {
+        env->ttmr |= TTMR_IP;
+        env->interrupt_request |= CPU_INTERRUPT_TIMER;
+    }
+
+    switch (env->ttmr & TTMR_M) {
+    case TIMER_NONE:
+        break;
+    case TIMER_INTR:
+        env->ttcr = 0;
+        count_start(env);
+        break;
+    case TIMER_SHOT:
+        count_stop(env);
+        break;
+    case TIMER_CONT:
+        count_start(env);
+        break;
+    }
+}
+
+void cpu_openrisc_clock_init(CPUOpenRISCState *env)
+{
+    env->timer = qemu_new_timer_ns(vm_clock, &openrisc_timer_cb, env);
+    env->ttmr = 0;
+    env->ttcr = 0;
+}