From patchwork Mon Jun 18 01:03:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 165375 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4380AB72B8 for ; Mon, 18 Jun 2012 12:00:06 +1000 (EST) Received: from localhost ([::1]:37393 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOt-000322-PY for incoming@patchwork.ozlabs.org; Sun, 17 Jun 2012 21:05:03 -0400 Received: from eggs.gnu.org ([208.118.235.92]:39726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOk-0002ud-EC for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SgQOi-00059J-NT for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:53 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:43016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOi-0004jq-Ez for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:52 -0400 Received: by mail-pz0-f45.google.com with SMTP id n2so5607657dad.4 for ; Sun, 17 Jun 2012 18:04:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=0cZ03O0CkcxICcgxzP58jp2j6tmwvbhtCJHBNSdYvvw=; b=K+JAhs+ody7BIFOXpH0bfoigssMsbkygRljBt8pZjh06POVouPdW5NE2/VnwZIHAXt AJYklbGqyOfH5CBIwVViLbqZCYgvxUjhwIyMC0vN8lhJdvVBsGXgPzXTwg1uMcSZJdkc 8Zf7JF06IpAI9YoJWbeyWcKxXYmxXNsFnMyr6dW+SEz7LRgJ7fVPjdPyjQ4GFR09mNeL +AMhF+xh324fTkwBZ3/NtI5N9bxbVU/h1iu22D0JOEuuhjJ48sRPd58g6SD/5bXpG/cw 8Z1IORpgKZ45d5G1yP9/MxcrhnQK+KCFBpcM+p4ojM+VEZLzXtkFuboQQQhWQ6MtZE9L dIoA== Received: by 10.68.232.232 with SMTP id tr8mr46090238pbc.73.1339981491475; Sun, 17 Jun 2012 18:04:51 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id ql3sm21880467pbc.72.2012.06.17.18.04.48 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 17 Jun 2012 18:04:50 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2012 09:03:01 +0800 Message-Id: <1339981384-9117-14-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1339981384-9117-1-git-send-email-proljc@gmail.com> References: <1339981384-9117-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH v5 13/16] target-or32: Add gdb stub support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add QEMU OpenRISC gdb stub support. Signed-off-by: Jia Liu --- gdbstub.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/gdbstub.c b/gdbstub.c index 08cf864..5d37dd9 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1155,6 +1155,68 @@ static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n) return sizeof(target_ulong); } +#elif defined(TARGET_OPENRISC) + +#define NUM_CORE_REGS (32 + 3) + +static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + GET_REG32(env->gpr[n]); + } else { + switch (n) { + case 32: /* PPC */ + GET_REG32(env->ppc); + break; + + case 33: /* NPC */ + GET_REG32(env->npc); + break; + + case 34: /* SR */ + GET_REG32(env->sr); + break; + + default: + break; + } + } + return 0; +} + +static int cpu_gdb_write_register(CPUOpenRISCState *env, + uint8_t *mem_buf, int n) +{ + uint32_t tmp; + + if (n > NUM_CORE_REGS) { + return 0; + } + + tmp = ldl_p(mem_buf); + + if (n < 32) { + env->gpr[n] = tmp; + } else { + switch (n) { + case 32: /* PPC */ + env->ppc = tmp; + break; + + case 33: /* NPC */ + env->npc = tmp; + break; + + case 34: /* SR */ + env->sr = tmp; + break; + + default: + break; + } + } + return 4; +} #elif defined (TARGET_SH4) /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ @@ -1924,6 +1986,8 @@ static void gdb_set_cpu_pc(GDBState *s, target_ulong pc) } #elif defined (TARGET_MICROBLAZE) s->c_cpu->sregs[SR_PC] = pc; +#elif defined(TARGET_OPENRISC) + s->c_cpu->pc = pc; #elif defined (TARGET_CRIS) s->c_cpu->pc = pc; #elif defined (TARGET_ALPHA)