From patchwork Mon Jun 18 01:02:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 165370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4F626B703E for ; Mon, 18 Jun 2012 11:30:18 +1000 (EST) Received: from localhost ([::1]:48135 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQnI-0001Nh-6a for incoming@patchwork.ozlabs.org; Sun, 17 Jun 2012 21:30:16 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50226) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOV-0002bm-Cw for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SgQOT-00057l-9F for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:38 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:43016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOT-0004jq-0e for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:37 -0400 Received: by mail-pz0-f45.google.com with SMTP id n2so5607657dad.4 for ; Sun, 17 Jun 2012 18:04:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=vKIjOKAIwAMsovaDIda0svvhuWPFSViuVwD4XZndlRA=; b=SsfU/wNOB99T0hFS4wSrOnBQHDRUq3qTG9jyC1heAAKrPQbnsy/msVQFnTFucORwgW AirQg7stWEXOjtjAsfv45nJxbH56ZIM6sAzpulg1Asmcu1koQ+TPvj3l49bjwjRdcDao GhD4EwLHuCbcNG/SJ0n+VjiprJxdmYfOdksTBGHQtP+5+Hblx6kGo8xM/ZOv+zlOrMoS 084Ya6UfQiLnqL1PCRXIyi6XX16NyZ+4BxNq2/PCRgN2YFHxCwIa9kOTLTQ7UbH7wpMj wC4fhjokVAOysrUMfwZHhDc3FIeOsqHbrCskQcOOi6FQNu64OU6U3aG1D+RuV6UucZ/Z T5UQ== Received: by 10.68.237.106 with SMTP id vb10mr27895153pbc.148.1339981476056; Sun, 17 Jun 2012 18:04:36 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id ql3sm21879794pbc.72.2012.06.17.18.04.32 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 17 Jun 2012 18:04:34 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2012 09:02:59 +0800 Message-Id: <1339981384-9117-12-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1339981384-9117-1-git-send-email-proljc@gmail.com> References: <1339981384-9117-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH v5 11/16] target-or32: Add a IIS dummy board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a dummy board for IIS. Signed-off-by: Jia Liu --- hw/openrisc/Makefile.objs | 2 +- hw/openrisc_sim.c | 145 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 hw/openrisc_sim.c diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs index 1c541a5..38ff8f5 100644 --- a/hw/openrisc/Makefile.objs +++ b/hw/openrisc/Makefile.objs @@ -1,3 +1,3 @@ -obj-y = openrisc_pic.o openrisc_timer.o +obj-y = openrisc_pic.o openrisc_sim.o openrisc_timer.o obj-y := $(addprefix ../,$(obj-y)) diff --git a/hw/openrisc_sim.c b/hw/openrisc_sim.c new file mode 100644 index 0000000..2fe27f5 --- /dev/null +++ b/hw/openrisc_sim.c @@ -0,0 +1,145 @@ +/* + * OpenRISC simulator for use as an ISS. + * + * Copyright (c) 2011-2012 Jia Liu + * Feng Gao + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "hw.h" +#include "openrisc_cpudev.h" +#include "boards.h" +#include "elf.h" +#include "pc.h" +#include "loader.h" +#include "exec-memory.h" +#include "sysemu.h" +#include "isa.h" +#include "qtest.h" + +#define KERNEL_LOAD_ADDR 0x100 + +static struct _loaderparams { + uint64_t ram_size; + const char *kernel_filename; + const char *kernel_cmdline; + const char *initrd_filename; +} loaderparams; + +static void main_cpu_reset(void *opaque) +{ + CPUOpenRISCState *env = opaque; + cpu_reset(ENV_GET_CPU(env)); +} + +static uint64_t openrisc_load_kernel(void) +{ + long kernel_size; + uint64_t elf_entry; + target_phys_addr_t entry; + + if (loaderparams.kernel_filename && !qtest_enabled()) { + kernel_size = load_elf(loaderparams.kernel_filename, NULL, NULL, + &elf_entry, NULL, NULL, 1, ELF_MACHINE, 1); + entry = elf_entry; + if (kernel_size < 0) { + kernel_size = load_uimage(loaderparams.kernel_filename, + &entry, NULL, NULL); + } + if (kernel_size < 0) { + kernel_size = load_image_targphys(loaderparams.kernel_filename, + KERNEL_LOAD_ADDR, + ram_size - KERNEL_LOAD_ADDR); + entry = KERNEL_LOAD_ADDR; + } + if (kernel_size < 0) { + fprintf(stderr, "qemu: could not load kernel '%s'\n", + loaderparams.kernel_filename); + exit(1); + } + + if (kernel_size > 0) { + return elf_entry; + } + } else { + entry = 0; + } + + return entry; +} + +static void openrisc_sim_init(ram_addr_t ram_size, + const char *boot_device, + const char *kernel_filename, + const char *kernel_cmdline, + const char *initrd_filename, + const char *cpu_model) +{ + CPUOpenRISCState *env; + MemoryRegion *ram = g_new(MemoryRegion, 1); + qemu_irq *i8259; + ISABus *isa_bus; + + if (!cpu_model) { + cpu_model = "or1200"; + } + env = cpu_init(cpu_model); + if (!env) { + fprintf(stderr, "Unable to find CPU definition!\n"); + exit(1); + } + + qemu_register_reset(main_cpu_reset, env); + main_cpu_reset(env); + + memory_region_init_ram(ram, "openrisc.ram", ram_size); + memory_region_add_subregion(get_system_memory(), 0, ram); + + if (kernel_filename) { + loaderparams.ram_size = ram_size; + loaderparams.kernel_filename = kernel_filename; + loaderparams.kernel_cmdline = kernel_cmdline; + env->pc = openrisc_load_kernel(); + } + + cpu_openrisc_pic_init(env); + cpu_openrisc_clock_init(env); + + isa_bus = isa_bus_new(NULL, get_system_io()); + i8259 = i8259_init(isa_bus, env->irq[3]); + isa_bus_irqs(isa_bus, i8259); + + serial_mm_init(get_system_memory(), 0x90000000, 0, + env->irq[2], 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + + if (nd_table[0].vlan) { + isa_ne2000_init(isa_bus, 0x92000000, 4, &nd_table[0]); + } +} + +static QEMUMachine openrisc_sim_machine = { + .name = "or32-sim", + .desc = "or32 simulation", + .init = openrisc_sim_init, + .max_cpus = 1, + .is_default = 1, +}; + +static void openrisc_sim_machine_init(void) +{ + qemu_register_machine(&openrisc_sim_machine); +} + +machine_init(openrisc_sim_machine_init);