From patchwork Mon Jun 18 01:03:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 165364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E9939B72B4 for ; Mon, 18 Jun 2012 11:04:57 +1000 (EST) Received: from localhost ([::1]:36917 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOl-0002m0-Pz for incoming@patchwork.ozlabs.org; Sun, 17 Jun 2012 21:04:55 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50247) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOd-0002g9-Ul for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SgQOb-00058d-CF for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:47 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:43016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SgQOa-0004jq-VB for qemu-devel@nongnu.org; Sun, 17 Jun 2012 21:04:45 -0400 Received: by mail-pz0-f45.google.com with SMTP id n2so5607657dad.4 for ; Sun, 17 Jun 2012 18:04:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=AXAaAgoKJsl+30roBPDXZr6FIMCgqLUb67WT18B2O68=; b=WnOIUplKOEMOb973XQUj10R4oIux2VFvMavMPn13FK4UPdnRrDCcargborTn9E7arV L7lRIffHqk5/crsjPcBdmGIt306LLTQT0/uGvEjyOsD1N05XiYZwkTyrmvLHfpgDGVXw z23k4CuF/EZp9ySiZegd91EbieBIaDohTp4lHi6ECi7vTkHMqNFNemLZuRcJykntqxd+ M6IPVnEgmyj8VCvxXu8oTt1S8Bxf6hQ5YsZ/PIWZ/Iod5qQFrzppbx2047kULKpKdtUn muGjdri3KdQ4KN355joZCAcFxZfba1BVwFy6VpmNzr1qyGVlVSZYqWuMl9NTn8Ma3C+j I5IQ== Received: by 10.68.231.229 with SMTP id tj5mr26090200pbc.39.1339981483974; Sun, 17 Jun 2012 18:04:43 -0700 (PDT) Received: from localhost ([1.202.183.51]) by mx.google.com with ESMTPS id hf5sm14263300pbc.4.2012.06.17.18.04.40 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 17 Jun 2012 18:04:42 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Mon, 18 Jun 2012 09:03:00 +0800 Message-Id: <1339981384-9117-13-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1339981384-9117-1-git-send-email-proljc@gmail.com> References: <1339981384-9117-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH v5 12/16] target-or32: Add system instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add OpenRISC system instruction support. Signed-off-by: Jia Liu --- target-openrisc/Makefile.objs | 3 +- target-openrisc/helper.h | 4 + target-openrisc/sys_helper.c | 233 +++++++++++++++++++++++++++++++++++++++++ target-openrisc/translate.c | 20 ++++ 4 files changed, 259 insertions(+), 1 deletion(-) create mode 100644 target-openrisc/sys_helper.c diff --git a/target-openrisc/Makefile.objs b/target-openrisc/Makefile.objs index 0d72c33..9d13a5d 100644 --- a/target-openrisc/Makefile.objs +++ b/target-openrisc/Makefile.objs @@ -1,3 +1,4 @@ obj-$(CONFIG_SOFTMMU) += machine.o obj-y += cpu.o excp.o intrpt.o mmu.o translate.o -obj-y += excp_helper.o fpu_helper.o int_helper.o intrpt_helper.o mmu_helper.o +obj-y += excp_helper.o fpu_helper.o int_helper.o intrpt_helper.o \ + mmu_helper.o sys_helper.o diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h index 60870f2..04c63c5 100644 --- a/target-openrisc/helper.h +++ b/target-openrisc/helper.h @@ -62,4 +62,8 @@ DEF_HELPER_FLAGS_1(fl1, 0, tl, tl) /* interrupt */ DEF_HELPER_FLAGS_1(rfe, 0, void, env) +/* sys */ +DEF_HELPER_FLAGS_4(mtspr, 0, void, env, tl, tl, tl) +DEF_HELPER_FLAGS_4(mfspr, 0, void, env, tl, tl, tl) + #include "def-helper.h" diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c new file mode 100644 index 0000000..f1e4314 --- /dev/null +++ b/target-openrisc/sys_helper.c @@ -0,0 +1,233 @@ +/* + * OpenRISC system instructions helper routines + * + * Copyright (c) 2011-2012 Jia Liu + * Zhizhou Zhang + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "cpu.h" +#include "helper.h" + +#define TO_SPR(group, number) (((group) << 11) + (number)) + +void HELPER(mtspr)(CPUOpenRISCState * env, + target_ulong ra, target_ulong rb, target_ulong offset) +{ +#if !defined(CONFIG_USER_ONLY) + int spr = (ra | offset); + int idx; + + switch (spr) { + case TO_SPR(0, 0): /* VR */ + env->vr = rb; + break; + + case TO_SPR(0, 16): /* NPC */ + env->npc = rb; + break; + + case TO_SPR(0, 17): /* SR */ + if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^ + (rb & (SR_IME | SR_DME | SR_SM))) { + tlb_flush(env, 1); + } + env->sr = rb; + env->sr |= SR_FO; /* FO is const equal to 1 */ + if (env->sr & SR_DME) { + env->tlb->map_address_data = &get_phys_data; + } else { + env->tlb->map_address_data = &get_phys_nommu; + } + + if (env->sr & SR_IME) { + env->tlb->map_address_code = &get_phys_code; + } else { + env->tlb->map_address_code = &get_phys_nommu; + } + break; + + case TO_SPR(0, 18): /* PPC */ + env->ppc = rb; + break; + + case TO_SPR(0, 32): /* EPCR */ + env->epcr = rb; + break; + + case TO_SPR(0, 48): /* EEAR */ + env->eear = rb; + break; + + case TO_SPR(0, 64): /* ESR */ + env->esr = rb; + break; + case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */ + idx = spr - TO_SPR(1, 512); + if (!(rb & 1)) { + tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK); + } + env->tlb->dtlb[0][idx].mr = rb; + break; + + case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */ + idx = spr - TO_SPR(1, 640); + env->tlb->dtlb[0][idx].tr = rb; + break; + case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ + case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ + case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ + case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ + case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ + case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ + break; + case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */ + idx = spr - TO_SPR(2, 512); + if (!(rb & 1)) { + tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK); + } + env->tlb->itlb[0][idx].mr = rb; + break; + + case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */ + idx = spr - TO_SPR(2, 640); + env->tlb->itlb[0][idx].tr = rb; + break; + case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ + case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ + case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ + case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ + case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ + case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ + break; + case TO_SPR(9, 0): /* PICMR */ + cpu_openrisc_store_picmr(env, rb); + break; + case TO_SPR(9, 2): /* PICSR */ + cpu_openrisc_store_picsr(env, rb); + break; + case TO_SPR(10, 0): /* TTMR */ + cpu_openrisc_store_compare(env, rb); + break; + case TO_SPR(10, 1): /* TTCR */ + cpu_openrisc_store_count(env, rb); + break; + default: + break; + } +#endif +} + +void HELPER(mfspr)(CPUOpenRISCState * env, + target_ulong rd, target_ulong ra, uint32_t offset) +{ +#if !defined(CONFIG_USER_ONLY) + int spr = env->gpr[ra] | offset; + int idx; + + switch (spr) { + case TO_SPR(0, 0): /* VR */ + env->gpr[rd] = (env->vr & SPR_VR); + break; + + case TO_SPR(0, 1): /* UPR */ + env->gpr[rd] = env->upr; /* TT, DM, IM, UP present */ + break; + + case TO_SPR(0, 2): /* CPUCFGR */ + env->gpr[rd] = env->cpucfgr; + break; + + case TO_SPR(0, 3): /* DMMUCFGR */ + env->gpr[rd] = env->dmmucfgr; /* 1Way, 64 entries */ + break; + case TO_SPR(0, 4): /* IMMUCFGR */ + env->gpr[rd] = env->immucfgr; + break; + + case TO_SPR(0, 16): /* NPC */ + env->gpr[rd] = env->npc; + break; + + case TO_SPR(0, 17): /* SR */ + env->gpr[rd] = env->sr; + break; + + case TO_SPR(0, 18): /* PPC */ + env->gpr[rd] = env->ppc; + break; + + case TO_SPR(0, 32): /* EPCR */ + env->gpr[rd] = env->epcr; + break; + + case TO_SPR(0, 48): /* EEAR */ + env->gpr[rd] = env->eear; + break; + + case TO_SPR(0, 64): /* ESR */ + env->gpr[rd] = env->esr; + break; + + case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */ + idx = spr - TO_SPR(1, 512); + env->gpr[rd] = env->tlb->dtlb[0][idx].mr; + break; + + case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */ + idx = spr - TO_SPR(1, 640); + env->gpr[rd] = env->tlb->dtlb[0][idx].tr; + break; + case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ + case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ + case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ + case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ + case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ + case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ + break; + + case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */ + idx = spr - TO_SPR(2, 512); + env->gpr[rd] = env->tlb->itlb[0][idx].mr; + break; + + case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */ + idx = spr - TO_SPR(2, 640); + env->gpr[rd] = env->tlb->itlb[0][idx].tr; + break; + case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ + case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ + case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ + case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ + case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ + case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ + break; + case TO_SPR(9, 0): /* PICMR */ + env->gpr[rd] = env->picmr; + break; + case TO_SPR(9, 2): /* PICSR */ + env->gpr[rd] = env->picsr; + break; + case TO_SPR(10, 0): /* TTMR */ + env->gpr[rd] = env->ttmr; + break; + case TO_SPR(10, 1): /* TTCR */ + env->gpr[rd] = cpu_openrisc_get_count(env); + break; + default: + break; + } +#endif +} diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index d4f894b..11eb0a5 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1241,10 +1241,30 @@ static void dec_misc(DisasContext *dc, CPUOpenRISCState *env, uint32_t insn) case 0x2d: /*l.mfspr*/ LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16); + { + TCGv_i32 ti = tcg_const_i32(I16); + TCGv td = tcg_const_tl(rd); + TCGv ta = tcg_const_tl(ra); + gen_helper_mfspr(cpu_env, td, ta, ti); + tcg_temp_free_i32(ti); + tcg_temp_free(td); + tcg_temp_free(ta); + } break; case 0x30: /*l.mtspr*/ LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11); + { + TCGv_i32 im = tcg_const_i32(tmp); + TCGv ta = tcg_temp_new(); + TCGv tb = tcg_temp_new(); + tcg_gen_mov_tl(ta, cpu_R[ra]); + tcg_gen_mov_tl(tb, cpu_R[rb]); + gen_helper_mtspr(cpu_env, ta, tb, im); + tcg_temp_free_i32(im); + tcg_temp_free(ta); + tcg_temp_free(tb); + } break; case 0x34: /*l.sd*/